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Message-Id: <20200311134115.13257-4-Eugeniy.Paltsev@synopsys.com>
Date: Wed, 11 Mar 2020 16:41:15 +0300
From: Eugeniy Paltsev <Eugeniy.Paltsev@...opsys.com>
To: linux-clk@...r.kernel.org
Cc: linux-kernel@...r.kernel.org, linux-snps-arc@...ts.infradead.org,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Alexey Brodkin <Alexey.Brodkin@...opsys.com>,
Eugeniy Paltsev <Eugeniy.Paltsev@...opsys.com>
Subject: [PATCH 3/3] CLK: HSDK: CGU: add support for 148.5MHz clock
Add support for 148.5MHz clock for HDMI PLL
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@...opsys.com>
---
drivers/clk/clk-hsdk-pll.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c
index 0ea7af57a5b1..b4f8852201cb 100644
--- a/drivers/clk/clk-hsdk-pll.c
+++ b/drivers/clk/clk-hsdk-pll.c
@@ -81,6 +81,7 @@ static const struct hsdk_pll_cfg asdt_pll_cfg[] = {
static const struct hsdk_pll_cfg hdmi_pll_cfg[] = {
{ 27000000, 0, 0, 0, 0, 1 },
+ { 148500000, 0, 21, 3, 0, 0 },
{ 297000000, 0, 21, 2, 0, 0 },
{ 540000000, 0, 19, 1, 0, 0 },
{ 594000000, 0, 21, 1, 0, 0 },
--
2.21.1
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