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Message-Id: <20200613024706.27975-3-alim.akhtar@samsung.com>
Date: Sat, 13 Jun 2020 08:16:58 +0530
From: Alim Akhtar <alim.akhtar@...sung.com>
To: robh@...nel.org
Cc: devicetree@...r.kernel.org, linux-scsi@...r.kernel.org,
krzk@...nel.org, avri.altman@....com, martin.petersen@...cle.com,
kwmad.kim@...sung.com, stanley.chu@...iatek.com,
cang@...eaurora.org, linux-samsung-soc@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
kishon@...com, Alim Akhtar <alim.akhtar@...sung.com>
Subject: [RESEND PATCH v10 02/10] scsi: ufs: add quirk to disallow reset of
interrupt aggregation
Some host controllers support interrupt aggregation but don't allow
resetting counter and timer in software.
Reviewed-by: Avri Altman <avri.altman@....com>
Signed-off-by: Seungwon Jeon <essuuj@...il.com>
Signed-off-by: Alim Akhtar <alim.akhtar@...sung.com>
---
drivers/scsi/ufs/ufshcd.c | 3 ++-
drivers/scsi/ufs/ufshcd.h | 6 ++++++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index 3655b88fc862..0e9704da58bd 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -4884,7 +4884,8 @@ static irqreturn_t ufshcd_transfer_req_compl(struct ufs_hba *hba)
* false interrupt if device completes another request after resetting
* aggregation and before reading the DB.
*/
- if (ufshcd_is_intr_aggr_allowed(hba))
+ if (ufshcd_is_intr_aggr_allowed(hba) &&
+ !(hba->quirks & UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR))
ufshcd_reset_intr_aggr(hba);
tr_doorbell = ufshcd_readl(hba, REG_UTP_TRANSFER_REQ_DOOR_BELL);
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 071f0edf3f64..53096642f9a8 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -523,6 +523,12 @@ enum ufshcd_quirks {
* Clear handling for transfer/task request list is just opposite.
*/
UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR = 1 << 6,
+
+ /*
+ * This quirk needs to be enabled if host controller doesn't allow
+ * that the interrupt aggregation timer and counter are reset by s/w.
+ */
+ UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR = 1 << 7,
};
enum ufshcd_caps {
--
2.17.1
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