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Message-Id: <d4c53dab6de5d5f70743d9c139d0117589530e62.1592210452.git-series.maxime@cerno.tech>
Date: Mon, 15 Jun 2020 10:40:52 +0200
From: Maxime Ripard <maxime@...no.tech>
To: Nicolas Saenz Julienne <nsaenzjulienne@...e.de>
Cc: linux-rpi-kernel@...ts.infradead.org,
bcm-kernel-feedback-list@...adcom.com,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Dave Stevenson <dave.stevenson@...pberrypi.com>,
Tim Gover <tim.gover@...pberrypi.com>,
Phil Elwell <phil@...pberrypi.com>,
Mike Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, linux-clk@...r.kernel.org,
Philipp Zabel <p.zabel@...gutronix.de>,
Maxime Ripard <maxime@...no.tech>
Subject: [PATCH v5 12/27] clk: bcm: rpi: Use CCF boundaries instead of rolling our own
The raspberrypi firmware clock driver has a min_rate / max_rate clamping by
storing the info it needs in a private structure.
However, the CCF already provides such a facility, so we can switch to it
to remove the boilerplate.
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@...e.de>
Tested-by: Nicolas Saenz Julienne <nsaenzjulienne@...e.de>
Signed-off-by: Maxime Ripard <maxime@...no.tech>
---
drivers/clk/bcm/clk-raspberrypi.c | 18 ++++++++----------
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/bcm/clk-raspberrypi.c b/drivers/clk/bcm/clk-raspberrypi.c
index a20492fade6a..e135ad28d38d 100644
--- a/drivers/clk/bcm/clk-raspberrypi.c
+++ b/drivers/clk/bcm/clk-raspberrypi.c
@@ -36,9 +36,6 @@ struct raspberrypi_clk {
struct rpi_firmware *firmware;
struct platform_device *cpufreq;
- unsigned long min_rate;
- unsigned long max_rate;
-
struct clk_hw pllb;
};
@@ -142,13 +139,11 @@ static int raspberrypi_fw_pll_set_rate(struct clk_hw *hw, unsigned long rate,
static int raspberrypi_pll_determine_rate(struct clk_hw *hw,
struct clk_rate_request *req)
{
- struct raspberrypi_clk *rpi = container_of(hw, struct raspberrypi_clk,
- pllb);
u64 div, final_rate;
u32 ndiv, fdiv;
/* We can't use req->rate directly as it would overflow */
- final_rate = clamp(req->rate, rpi->min_rate, rpi->max_rate);
+ final_rate = clamp(req->rate, req->min_rate, req->max_rate);
div = (u64)final_rate << A2W_PLL_FRAC_BITS;
do_div(div, req->best_parent_rate);
@@ -215,12 +210,15 @@ static int raspberrypi_register_pllb(struct raspberrypi_clk *rpi)
dev_info(rpi->dev, "CPU frequency range: min %u, max %u\n",
min_rate, max_rate);
- rpi->min_rate = min_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
- rpi->max_rate = max_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE;
-
rpi->pllb.init = &init;
- return devm_clk_hw_register(rpi->dev, &rpi->pllb);
+ ret = devm_clk_hw_register(rpi->dev, &rpi->pllb);
+ if (!ret)
+ clk_hw_set_rate_range(&rpi->pllb,
+ min_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE,
+ max_rate * RPI_FIRMWARE_PLLB_ARM_DIV_RATE);
+
+ return ret;
}
static struct clk_fixed_factor raspberrypi_clk_pllb_arm = {
--
git-series 0.9.1
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