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Message-ID: <DM5PR12MB1276C95C5A57B462FD64B2B4DA9A0@DM5PR12MB1276.namprd12.prod.outlook.com>
Date: Wed, 17 Jun 2020 21:14:08 +0000
From: Gustavo Pimentel <Gustavo.Pimentel@...opsys.com>
To: Vidya Sagar <vidyas@...dia.com>,
"jingoohan1@...il.com" <jingoohan1@...il.com>,
"lorenzo.pieralisi@....com" <lorenzo.pieralisi@....com>,
"bhelgaas@...gle.com" <bhelgaas@...gle.com>,
"amurray@...goodpenguin.co.uk" <amurray@...goodpenguin.co.uk>,
"robh@...nel.org" <robh@...nel.org>,
"thierry.reding@...il.com" <thierry.reding@...il.com>,
"jonathanh@...dia.com" <jonathanh@...dia.com>,
"alan.mikhak@...ive.com" <alan.mikhak@...ive.com>,
"kishon@...com" <kishon@...com>
CC: "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"kthota@...dia.com" <kthota@...dia.com>,
"mmaddireddy@...dia.com" <mmaddireddy@...dia.com>,
"sagar.tv@...il.com" <sagar.tv@...il.com>
Subject: RE: [PATCH 0/2] PCI: dwc: Add support to handle prefetchable memory
separately
On Wed, Jun 17, 2020 at 19:56:34, Vidya Sagar <vidyas@...dia.com> wrote:
>
>
> On 02-Jun-20 10:37 PM, Gustavo Pimentel wrote:
> > External email: Use caution opening links or attachments
> >
> >
> > On Tue, Jun 2, 2020 at 11:9:38, Vidya Sagar <vidyas@...dia.com> wrote:
> >
> >> In this patch series,
> >> Patch-1
> >> adds required infrastructure to deal with prefetchable memory region
> >> information coming from 'ranges' property of the respective device-tree node
> >> separately from non-prefetchable memory region information.
> >> Patch-2
> >> Adds support to use ATU region-3 for establishing the mapping between CPU
> >> addresses and PCIe bus addresses.
> >> It also changes the logic to determine whether mapping is required or not by
> >> checking both CPU address and PCIe bus address for both prefetchable and
> >> non-prefetchable regions. If the addresses are same, then, it is understood
> >> that 1:1 mapping is in place and there is no need to setup ATU mapping
> >> whereas if the addresses are not the same, then, there is a need to setup ATU
> >> mapping. This is certainly true for Tegra194 and what I heard from our HW
> >> engineers is that it should generally be true for any DWC based implementation
> >> also.
> >> Hence, I request Synopsys folks (Jingoo Han & Gustavo Pimentel ??) to confirm
> >> the same so that this particular patch won't cause any regressions for other
> >> DWC based platforms.
> >
> > Hi Vidya,
> >
> > Unfortunately due to the COVID-19 lockdown, I can't access my development
> > prototype setup to test your patch.
> > It might take some while until I get the possibility to get access to it
> > again.
> Hi Gustavo,
> Did you find time to check this?
> Adding Kishon and Alan as well to take a look at this and verify on
> their platforms if possible.
My site is still in lockdown, there is no date to return to the office.
Sorry.
-Gustavo
>
> Thanks,
> Vidya Sagar
>
> >
> > -Gustavo
> >
> >>
> >> Vidya Sagar (2):
> >> PCI: dwc: Add support to handle prefetchable memory separately
> >> PCI: dwc: Use ATU region to map prefetchable memory region
> >>
> >> .../pci/controller/dwc/pcie-designware-host.c | 46 ++++++++++++++-----
> >> drivers/pci/controller/dwc/pcie-designware.c | 6 ++-
> >> drivers/pci/controller/dwc/pcie-designware.h | 8 +++-
> >> 3 files changed, 45 insertions(+), 15 deletions(-)
> >>
> >> --
> >> 2.17.1
> >
> >
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