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Date:   Mon, 6 Jul 2020 10:05:06 +0530
From:   Vidya Sagar <vidyas@...dia.com>
To:     Gustavo Pimentel <Gustavo.Pimentel@...opsys.com>,
        "jingoohan1@...il.com" <jingoohan1@...il.com>,
        "lorenzo.pieralisi@....com" <lorenzo.pieralisi@....com>,
        "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
        "amurray@...goodpenguin.co.uk" <amurray@...goodpenguin.co.uk>,
        "robh@...nel.org" <robh@...nel.org>,
        "thierry.reding@...il.com" <thierry.reding@...il.com>,
        "jonathanh@...dia.com" <jonathanh@...dia.com>,
        <alan.mikhak@...ive.com>, <kishon@...com>
CC:     "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "kthota@...dia.com" <kthota@...dia.com>,
        "mmaddireddy@...dia.com" <mmaddireddy@...dia.com>,
        "sagar.tv@...il.com" <sagar.tv@...il.com>
Subject: Re: [PATCH 0/2] PCI: dwc: Add support to handle prefetchable memory
 separately



On 18-Jun-20 12:26 AM, Vidya Sagar wrote:
> 
> 
> On 02-Jun-20 10:37 PM, Gustavo Pimentel wrote:
>> External email: Use caution opening links or attachments
>>
>>
>> On Tue, Jun 2, 2020 at 11:9:38, Vidya Sagar <vidyas@...dia.com> wrote:
>>
>>> In this patch series,
>>> Patch-1
>>> adds required infrastructure to deal with prefetchable memory region
>>> information coming from 'ranges' property of the respective 
>>> device-tree node
>>> separately from non-prefetchable memory region information.
>>> Patch-2
>>> Adds support to use ATU region-3 for establishing the mapping between 
>>> CPU
>>> addresses and PCIe bus addresses.
>>> It also changes the logic to determine whether mapping is required or 
>>> not by
>>> checking both CPU address and PCIe bus address for both prefetchable and
>>> non-prefetchable regions. If the addresses are same, then, it is 
>>> understood
>>> that 1:1 mapping is in place and there is no need to setup ATU mapping
>>> whereas if the addresses are not the same, then, there is a need to 
>>> setup ATU
>>> mapping. This is certainly true for Tegra194 and what I heard from 
>>> our HW
>>> engineers is that it should generally be true for any DWC based 
>>> implementation
>>> also.
>>> Hence, I request Synopsys folks (Jingoo Han & Gustavo Pimentel ??) to 
>>> confirm
>>> the same so that this particular patch won't cause any regressions 
>>> for other
>>> DWC based platforms.
>>
>> Hi Vidya,
>>
>> Unfortunately due to the COVID-19 lockdown, I can't access my development
>> prototype setup to test your patch.
>> It might take some while until I get the possibility to get access to it
>> again.
> Hi Gustavo,
> Did you find time to check this?
> Adding Kishon and Alan as well to take a look at this and verify on 
> their platforms if possible.
Hi Kishon and Alan, did you find time to verify this on your respective 
platforms?

Thanks,
Vidya Sagar
> 
> Thanks,
> Vidya Sagar
> 
>>
>> -Gustavo
>>
>>>
>>> Vidya Sagar (2):
>>>    PCI: dwc: Add support to handle prefetchable memory separately
>>>    PCI: dwc: Use ATU region to map prefetchable memory region
>>>
>>>   .../pci/controller/dwc/pcie-designware-host.c | 46 ++++++++++++++-----
>>>   drivers/pci/controller/dwc/pcie-designware.c  |  6 ++-
>>>   drivers/pci/controller/dwc/pcie-designware.h  |  8 +++-
>>>   3 files changed, 45 insertions(+), 15 deletions(-)
>>>
>>> -- 
>>> 2.17.1
>>
>>

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