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Message-ID: <20200617162740.GA4181112@x1>
Date: Wed, 17 Jun 2020 18:27:40 +0200
From: Drew Fustini <drew@...gleboard.org>
To: Tony Lindgren <tony@...mide.com>
Cc: Grygorii Strashko <grygorii.strashko@...com>,
linux-omap@...r.kernel.org, linux-kernel@...r.kernel.org,
Benoît Cousson <bcousson@...libre.com>,
Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org,
Santosh Shilimkar <ssantosh@...nel.org>,
Suman Anna <s-anna@...com>,
Haojian Zhuang <haojian.zhuang@...aro.org>,
Linus Walleij <linus.walleij@...aro.org>,
linux-gpio@...r.kernel.org, jkridner@...gleboard.org,
robertcnelson@...il.com
Subject: Re: [PATCH] ARM: dts: AM33xx-l4: add gpio-ranges
On Tue, Jun 02, 2020 at 06:34:58PM +0200, Drew Fustini wrote:
> On Tue, Jun 02, 2020 at 06:51:55AM -0700, Tony Lindgren wrote:
> > * Grygorii Strashko <grygorii.strashko@...com> [200602 13:44]:
> > >
> > >
> > > On 02/06/2020 16:14, Drew Fustini wrote:
> > > > Add gpio-ranges properties to the gpio controller nodes.
> > > >
> > > > These gpio-ranges were created based on "Table 9-10. CONTROL_MODULE
> > > > REGISTERS" in the "AM335x Technical Reference Manual" [0] and "Table
> > > > 4-2. Pin Attributes" in the "AM335x Sitara Processor datasheet" [1].
> > > > A csv file with this data is available for reference [2].
> > >
> > > It will be good if you can explain not only "what" is changed, but
> > > also "why" it's needed in commit message.
> >
> > Also, please check (again) that this is the same for all the am3
> > variants. For omap3, we had different pad assignments even between
> > SoC revisions. Different pad routings should be easy to deal with
> > in the dts if needed though.
> >
> > Regards,
> >
> > Tony
>
> It appears that the only usage of am33xx-l4.dtsi is for am335x for which
> specific parts mentioned in those dtsi files are 3352, 3358, and 3359.
>
> $ git grep am33xx-l4.dtsi
> arch/arm/boot/dts/am33xx.dtsi:#include "am33xx-l4.dtsi"
> $ git grep -l '#include "am33xx.dtsi"' arch/ |wc -l
> 27
> $ git grep -l '#include "am33xx.dtsi"' arch/ |grep -v am335x |wc -l
> 0
>
> Also, it appears that the only AM33xx parts that actually exist are [0]:
>
> AM3351, AM3352, AM3354, AM3356, AM3357, AM3358, AM3359
>
> I clicked on the datasheet link for each product page and while the URL
> has the specific part number in it [1], they all end up loading the
> exact same PDF. The header states:
>
> "AM3359, AM3358, AM3357, AM3356, AM3354, AM3352, AM3351
> SPRS717L – OCTOBER 2011 – REVISED MARCH 2020"
>
> Thus, I do believe all SoC's using am33xx-l4.dtsi would have the same
> memory map for the pin control registers and the same relationshop from
> pin to gpio line. For example, GPMC_A0 has mode 7 and it is labeled
> gpio1_16. conf_gpmc_a0 is at offset 840h which makes it pin 16.
>
> Maybe am33xx-l4.dtsi should have actually been named am335x-l4.dtsi?
>
> Though I suppose there is no point in changing that now.
>
> thanks,
> drew
>
> [0] http://www.ti.com/processors/sitara-arm/am335x-cortex-a8/overview.html
> [1] https://www.ti.com/lit/ds/symlink/am3359.pdf
Tony -
These gpio-ranges are correct for all the platforms that included
am33xx-l4.dtsi.
I think it makes sense to add gpio-ranges properties as they describe
the relationship between a gpio line and pin control register that
exists in the hardware.
Are there changes you would like to see in this patch?
Thanks,
Drew
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