linux-kernel - [PATCH 5.7 326/376] memory: samsung: exynos5422-dmc: Fix tFAW timings alignment

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <20200619141725.764504538@linuxfoundation.org>
Date:   Fri, 19 Jun 2020 16:34:04 +0200
From:   Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To:     linux-kernel@...r.kernel.org
Cc:     Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        stable@...r.kernel.org, Bernard Zhao <bernard@...o.com>,
        Lukasz Luba <lukasz.luba@....com>,
        Krzysztof Kozlowski <krzk@...nel.org>
Subject: [PATCH 5.7 326/376] memory: samsung: exynos5422-dmc: Fix tFAW timings alignment

From: Bernard Zhao <bernard@...o.com>

commit 4bff7214d263b5235263136cb53147a759b3f3ab upstream.

Aligning of tFAW timing with standard was using wrong argument as
minimum acceptable value.  This could lead to wrong timing if provided
timings and clock period do not match the standard.

Fixes: 6e7674c3c6df ("memory: Add DMC driver for Exynos5422")
Cc: <stable@...r.kernel.org>
Signed-off-by: Bernard Zhao <bernard@...o.com>
Reviewed-by: Lukasz Luba <lukasz.luba@....com>
Signed-off-by: Krzysztof Kozlowski <krzk@...nel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org>

---
 drivers/memory/samsung/exynos5422-dmc.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- a/drivers/memory/samsung/exynos5422-dmc.c
+++ b/drivers/memory/samsung/exynos5422-dmc.c
@@ -1091,7 +1091,7 @@ static int create_timings_aligned(struct
 	/* power related timings */
 	val = dmc->timings->tFAW / clk_period_ps;
 	val += dmc->timings->tFAW % clk_period_ps ? 1 : 0;
-	val = max(val, dmc->min_tck->tXP);
+	val = max(val, dmc->min_tck->tFAW);
 	reg = &timing_power[0];
 	*reg_timing_power |= TIMING_VAL2REG(reg, val);