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Message-ID: <20200623162751.GA4846@lst.de>
Date: Tue, 23 Jun 2020 18:27:51 +0200
From: Christoph Hellwig <hch@....de>
To: Baolin Wang <baolin.wang@...ux.alibaba.com>
Cc: kbusch@...nel.org, axboe@...com, hch@....de, sagi@...mberg.me,
baolin.wang7@...il.com, linux-nvme@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/3] nvme-pci: Add controller memory buffer supported
macro
On Tue, Jun 23, 2020 at 09:24:33PM +0800, Baolin Wang wrote:
> Introduce a new capability macro to indicate if the controller
> supports the memory buffer or not, instead of reading the
> NVME_REG_CMBSZ register.
This is a complex issue. The CMBS bit was only added in NVMe 1.4 as
a backwards incompatible change, as the CMB addressing scheme can lead
to data corruption. The CMBS was added as part of the horribe hack
that also involves the CBA field, which we'll need to see before
using it to work around the addressing issue. At the same time we
should also continue supporting the legacy pre-1.4 CMB with a warning
(and may reject it if we know we run in a VM).
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