| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Tue, 23 Jun 2020 16:21:44 -0700
From: Bjorn Andersson <bjorn.andersson@...aro.org>
To: Konrad Dybcio <konradybcio@...il.com>
Cc: skrzynka@...radybcio.pl, Andy Gross <agross@...nel.org>,
Rob Herring <robh+dt@...nel.org>,
Kees Cook <keescook@...omium.org>,
Anton Vorontsov <anton@...msg.org>,
Colin Cross <ccross@...roid.com>,
Tony Luck <tony.luck@...el.com>, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 07/12] arm64: dts: qcom: msm8994: Add I2C, SPI and
BLSP DMA nodes
On Tue 23 Jun 15:48 PDT 2020, Konrad Dybcio wrote:
> Add support for I2C and SPI buses to enable peripherals
> such as touchscreens or sensors. Also add DMA nodes,
> configuration and BLSP2 UART2 interface.
>
> Signed-off-by: Konrad Dybcio <konradybcio@...il.com>
Applied, thanks
> ---
> arch/arm64/boot/dts/qcom/msm8994.dtsi | 156 +++++++++++++++++++++++++-
> 1 file changed, 155 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi
> index 838ffc0d9c16..8af01ebe73f7 100644
> --- a/arch/arm64/boot/dts/qcom/msm8994.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi
> @@ -365,14 +365,168 @@ sdhc1: sdhci@...24900 {
> status = "disabled";
> };
>
> + blsp1_dma: dma@...04000 {
> + compatible = "qcom,bam-v1.7.0";
> + reg = <0xf9904000 0x19000>;
> + interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "bam_clk";
> + #dma-cells = <1>;
> + qcom,ee = <0>;
> + qcom,controlled-remotely;
> + num-channels = <18>;
> + qcom,num-ees = <4>;
> + };
> +
> blsp1_uart2: serial@...1e000 {
> compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> reg = <0xf991e000 0x1000>;
> interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
> - status = "disabled";
> clock-names = "core", "iface";
> clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
> <&gcc GCC_BLSP1_AHB_CLK>;
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&blsp1_uart2_default>;
> + pinctrl-1 = <&blsp1_uart2_sleep>;
> + status = "disabled";
> + };
> +
> + blsp_i2c1: i2c@...23000 {
> + compatible = "qcom,i2c-qup-v2.2.1";
> + reg = <0xf9923000 0x500>;
> + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_AHB_CLK>,
> + <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
> + clock-names = "iface", "core";
> + clock-frequency = <400000>;
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&i2c1_default>;
> + pinctrl-1 = <&i2c1_sleep>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + blsp_spi0: spi@...23000 {
> + compatible = "qcom,spi-qup-v2.2.1";
> + reg = <0xf9923000 0x500>;
> + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
> + <&gcc GCC_BLSP1_AHB_CLK>;
> + clock-names = "core", "iface";
> + spi-max-frequency = <19200000>;
> + dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
> + dma-names = "tx", "rx";
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&blsp1_spi0_default>;
> + pinctrl-1 = <&blsp1_spi0_sleep>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + blsp_i2c2: i2c@...24000 {
> + compatible = "qcom,i2c-qup-v2.2.1";
> + reg = <0xf9924000 0x500>;
> + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_AHB_CLK>,
> + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
> + clock-names = "iface", "core";
> + clock-frequency = <355000>;
> + dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
> + dma-names = "tx", "rx";
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&i2c2_default>;
> + pinctrl-1 = <&i2c2_sleep>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + /* I2C3 doesn't exist */
> +
> + blsp_i2c4: i2c@...26000 {
> + compatible = "qcom,i2c-qup-v2.2.1";
> + reg = <0xf9926000 0x500>;
> + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_AHB_CLK>,
> + <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
> + clock-names = "iface", "core";
> + clock-frequency = <355000>;
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&i2c4_default>;
> + pinctrl-1 = <&i2c4_sleep>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + blsp2_dma: dma@...44000 {
> + compatible = "qcom,bam-v1.7.0";
> + reg = <0xf9944000 0x19000>;
> + interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP2_AHB_CLK>;
> + clock-names = "bam_clk";
> + #dma-cells = <1>;
> + qcom,ee = <0>;
> + qcom,controlled-remotely;
> + num-channels = <18>;
> + qcom,num-ees = <4>;
> + };
> +
> + /* According to downstream kernels, i2c6
> + * comes before i2c5 address-wise...
> + */
> +
> + blsp_i2c6: i2c@...28000 {
> + compatible = "qcom,i2c-qup-v2.2.1";
> + reg = <0xf9928000 0x500>;
> + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP1_AHB_CLK>,
> + <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
> + clock-names = "iface", "core";
> + clock-frequency = <355000>;
> + dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
> + dma-names = "tx", "rx";
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&i2c6_default>;
> + pinctrl-1 = <&i2c6_sleep>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + blsp2_uart2: serial@...5e000 {
> + compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
> + reg = <0xf995e000 0x1000>;
> + interrupts = <GIC_SPI 146 IRQ_TYPE_EDGE_FALLING>;
> + clock-names = "core", "iface";
> + clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
> + <&gcc GCC_BLSP2_AHB_CLK>;
> + dmas = <&blsp2_dma 2>, <&blsp2_dma 3>;
> + dma-names = "tx", "rx";
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&blsp2_uart2_default>;
> + pinctrl-1 = <&blsp2_uart2_sleep>;
> + status = "disabled";
> + };
> +
> + blsp_i2c5: i2c@...67000 {
> + compatible = "qcom,i2c-qup-v2.2.1";
> + reg = <0xf9967000 0x500>;
> + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&gcc GCC_BLSP2_AHB_CLK>,
> + <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
> + clock-names = "iface", "core";
> + clock-frequency = <355000>;
> + dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
> + dma-names = "tx", "rx";
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&i2c5_default>;
> + pinctrl-1 = <&i2c5_sleep>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> };
>
> gcc: clock-controller@...00000 {
> --
> 2.27.0
>
Powered by blists - more mailing lists