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Message-Id: <20200702201633.22693-5-tn@semihalf.com>
Date: Thu, 2 Jul 2020 22:16:33 +0200
From: Tomasz Nowicki <tn@...ihalf.com>
To: will@...nel.org, robin.murphy@....com, joro@...tes.org,
gregory.clement@...tlin.com, robh+dt@...nel.org, hannah@...vell.com
Cc: linux-kernel@...r.kernel.org, iommu@...ts.linux-foundation.org,
devicetree@...r.kernel.org, catalin.marinas@....com,
nadavh@...vell.com, linux-arm-kernel@...ts.infradead.org,
mw@...ihalf.com, Tomasz Nowicki <tn@...ihalf.com>
Subject: [PATCH v3 4/4] arm64: dts: marvell: add SMMU support
From: Marcin Wojtas <mw@...ihalf.com>
Add IOMMU node for Marvell AP806 based SoCs together with platform
and PCI device Stream ID mapping.
Signed-off-by: Marcin Wojtas <mw@...ihalf.com>
Signed-off-by: Tomasz Nowicki <tn@...ihalf.com>
---
arch/arm64/boot/dts/marvell/armada-8040.dtsi | 36 +++++++++++++++++++
arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 17 +++++++++
2 files changed, 53 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-8040.dtsi b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
index 7699b19224c2..25c1df709f72 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
@@ -23,3 +23,39 @@
&cp0_rtc {
status = "disabled";
};
+
+&cp0_usb3_0 {
+ iommus = <&smmu 0x440>;
+};
+
+&cp0_usb3_1 {
+ iommus = <&smmu 0x441>;
+};
+
+&cp0_sata0 {
+ iommus = <&smmu 0x444>;
+};
+
+&cp0_sdhci0 {
+ iommus = <&smmu 0x445>;
+};
+
+&cp1_sata0 {
+ iommus = <&smmu 0x454>;
+};
+
+&cp1_usb3_0 {
+ iommus = <&smmu 0x450>;
+};
+
+&cp1_usb3_1 {
+ iommus = <&smmu 0x451>;
+};
+
+&cp0_pcie0 {
+ iommu-map =
+ <0x0 &smmu 0x480 0x20>,
+ <0x100 &smmu 0x4a0 0x20>,
+ <0x200 &smmu 0x4c0 0x20>;
+ iommu-map-mask = <0x031f>;
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
index 7f9b9a647717..ded8b8082d79 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
@@ -56,6 +56,23 @@
compatible = "simple-bus";
ranges = <0x0 0x0 0xf0000000 0x1000000>;
+ smmu: iommu@...0000 {
+ compatible = "marvell,ap806-smmu-500", "arm,mmu-500";
+ reg = <0x100000 0x100000>;
+ dma-coherent;
+ #iommu-cells = <1>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
gic: interrupt-controller@...000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
--
2.17.1
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