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Message-Id: <20200702201633.22693-4-tn@semihalf.com>
Date:   Thu,  2 Jul 2020 22:16:32 +0200
From:   Tomasz Nowicki <tn@...ihalf.com>
To:     will@...nel.org, robin.murphy@....com, joro@...tes.org,
        gregory.clement@...tlin.com, robh+dt@...nel.org, hannah@...vell.com
Cc:     linux-kernel@...r.kernel.org, iommu@...ts.linux-foundation.org,
        devicetree@...r.kernel.org, catalin.marinas@....com,
        nadavh@...vell.com, linux-arm-kernel@...ts.infradead.org,
        mw@...ihalf.com, Tomasz Nowicki <tn@...ihalf.com>
Subject: [PATCH v3 3/4] dt-bindings: arm-smmu: add compatible string for Marvell Armada-AP806 SMMU-500

Add specific compatible string for Marvell usage due to errata of
accessing 64bits registers of ARM SMMU, in AP806.

AP806 SoC uses the generic ARM-MMU500, and there's no specific
implementation of Marvell, this compatible is used for errata only.

Signed-off-by: Hanna Hawa <hannah@...vell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@...tlin.com>
Signed-off-by: Tomasz Nowicki <tn@...ihalf.com>
---
 Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index d7ceb4c34423..7beca9c00b12 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -38,6 +38,11 @@ properties:
               - qcom,sc7180-smmu-500
               - qcom,sdm845-smmu-500
           - const: arm,mmu-500
+      - description: Marvell SoCs implementing "arm,mmu-500"
+        items:
+          - enum:
+              - marvell,ap806-smmu-500
+          - const: arm,mmu-500
       - items:
           - const: arm,mmu-500
           - const: arm,smmu-v2
-- 
2.17.1

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