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Date: Fri, 3 Jul 2020 12:24:38 +0800
From: kernel test robot <lkp@...el.com>
To: Vinay Simha BN <simhavcs@...il.com>
Cc: kbuild-all@...ts.01.org, clang-built-linux@...glegroups.com,
Vinay Simha BN <simhavcs@...il.com>,
Andrzej Hajda <a.hajda@...sung.com>,
Neil Armstrong <narmstrong@...libre.com>,
Laurent Pinchart <Laurent.pinchart@...asonboard.com>,
Jonas Karlman <jonas@...boo.se>,
Jernej Skrabec <jernej.skrabec@...l.net>,
David Airlie <airlied@...ux.ie>,
Daniel Vetter <daniel@...ll.ch>,
open list <linux-kernel@...r.kernel.org>,
"open list:DRM DRIVERS" <dri-devel@...ts.freedesktop.org>
Subject: Re: [PATCH v6 2/2] display/drm/bridge: TC358775 DSI/LVDS driver
Hi Vinay,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[also build test WARNING on v5.8-rc3 next-20200702]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Vinay-Simha-BN/dt-binding-Add-DSI-LVDS-TC358775-bridge-bindings/20200702-203915
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git cd77006e01b3198c75fb7819b3d0ff89709539bb
config: x86_64-allyesconfig (attached as .config)
compiler: clang version 11.0.0 (https://github.com/llvm/llvm-project 003a086ffc0d1affbb8300b36225fb8150a2d40a)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install x86_64 cross compiling tool for clang build
# apt-get install binutils-x86-64-linux-gnu
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@...el.com>
All warnings (new ones prefixed by >>):
>> drivers/gpu/drm/bridge/tc358775.c:457:2: warning: variable 'bpc' is used uninitialized whenever switch default is taken [-Wsometimes-uninitialized]
default:
^~~~~~~
drivers/gpu/drm/bridge/tc358775.c:464:34: note: uninitialized use occurs here
dsiclk = mode->crtc_clock * 3 * bpc / tc->num_dsi_lanes / 1000;
^~~
drivers/gpu/drm/bridge/tc358775.c:387:14: note: initialize the variable 'bpc' to silence this warning
u8 link, bpc;
^
= '\0'
>> drivers/gpu/drm/bridge/tc358775.c:527:1: warning: no previous prototype for function 'tc_mode_valid' [-Wmissing-prototypes]
tc_mode_valid(struct drm_bridge *bridge,
^
drivers/gpu/drm/bridge/tc358775.c:526:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
enum drm_mode_status
^
static
drivers/gpu/drm/bridge/tc358775.c:566:8: warning: variable 'len' is used uninitialized whenever 'if' condition is false [-Wsometimes-uninitialized]
if (endpoint) {
^~~~~~~~
drivers/gpu/drm/bridge/tc358775.c:579:22: note: uninitialized use occurs here
tc->num_dsi_lanes = len / sizeof(u32);
^~~
drivers/gpu/drm/bridge/tc358775.c:566:4: note: remove the 'if' if its condition is always true
if (endpoint) {
^~~~~~~~~~~~~~
drivers/gpu/drm/bridge/tc358775.c:562:7: warning: variable 'len' is used uninitialized whenever 'if' condition is false [-Wsometimes-uninitialized]
if (parent) {
^~~~~~
drivers/gpu/drm/bridge/tc358775.c:579:22: note: uninitialized use occurs here
tc->num_dsi_lanes = len / sizeof(u32);
^~~
drivers/gpu/drm/bridge/tc358775.c:562:3: note: remove the 'if' if its condition is always true
if (parent) {
^~~~~~~~~~~~
drivers/gpu/drm/bridge/tc358775.c:558:6: warning: variable 'len' is used uninitialized whenever 'if' condition is false [-Wsometimes-uninitialized]
if (endpoint) {
^~~~~~~~
drivers/gpu/drm/bridge/tc358775.c:579:22: note: uninitialized use occurs here
tc->num_dsi_lanes = len / sizeof(u32);
^~~
drivers/gpu/drm/bridge/tc358775.c:558:2: note: remove the 'if' if its condition is always true
if (endpoint) {
^~~~~~~~~~~~~~
drivers/gpu/drm/bridge/tc358775.c:550:9: note: initialize the variable 'len' to silence this warning
int len;
^
= 0
drivers/gpu/drm/bridge/tc358775.c:662:16: error: incompatible function pointer types initializing 'enum drm_mode_status (*)(struct drm_bridge *, const struct drm_display_mode *)' with an expression of type 'enum drm_mode_status (struct drm_bridge *, const struct drm_display_info *, const struct drm_display_mode *)' [-Werror,-Wincompatible-function-pointer-types]
.mode_valid = tc_mode_valid,
^~~~~~~~~~~~~
5 warnings and 1 error generated.
vim +/bpc +457 drivers/gpu/drm/bridge/tc358775.c
379
380 static void tc_bridge_enable(struct drm_bridge *bridge)
381 {
382 struct tc_data *tc = bridge_to_tc(bridge);
383 u32 hback_porch, hsync_len, hfront_porch, hactive, htime1, htime2;
384 u32 vback_porch, vsync_len, vfront_porch, vactive, vtime1, vtime2;
385 u32 val = 0, val_lvcfg = 0;
386 u16 dsiclk, clkdiv, byteclk, t1, t2, t3, vsdelay;
387 u8 link, bpc;
388 u16 bus_formats;
389 struct drm_display_mode *mode;
390 struct drm_connector *connector = get_connector(bridge->encoder);
391
392 mode = &bridge->encoder->crtc->state->adjusted_mode;
393
394 hback_porch = mode->htotal - mode->hsync_end;
395 hsync_len = mode->hsync_end - mode->hsync_start;
396 vback_porch = mode->vtotal - mode->vsync_end;
397 vsync_len = mode->vsync_end - mode->vsync_start;
398
399 htime1 = (hback_porch << 16) + hsync_len;
400 vtime1 = (vback_porch << 16) + vsync_len;
401
402 hfront_porch = mode->hsync_start - mode->hdisplay;
403 hactive = mode->hdisplay;
404 vfront_porch = mode->vsync_start - mode->vdisplay;
405 vactive = mode->vdisplay;
406
407 htime2 = (hfront_porch << 16) + hactive;
408 vtime2 = (vfront_porch << 16) + vactive;
409
410 val = d2l_read(tc->i2c, IDREG);
411
412 dev_info(tc->dev, "DSI2LVDS Chip ID.%02x Revision ID. %02x **\n",
413 (val >> 8) & 0xFF, val & 0xFF);
414
415 d2l_write(tc->i2c, SYSRST, SYS_RST_REG | SYS_RST_DSIRX | SYS_RST_BM |
416 SYS_RST_LCD | SYS_RST_I2CM | SYS_RST_I2CS);
417 usleep_range(30000, 40000);
418
419 d2l_write(tc->i2c, PPI_TX_RX_TA, TTA_GET | TTA_SURE);
420 d2l_write(tc->i2c, PPI_LPTXTIMECNT, LPX_PERIOD);
421 d2l_write(tc->i2c, PPI_D0S_CLRSIPOCOUNT, 3);
422 d2l_write(tc->i2c, PPI_D1S_CLRSIPOCOUNT, 3);
423 d2l_write(tc->i2c, PPI_D2S_CLRSIPOCOUNT, 3);
424 d2l_write(tc->i2c, PPI_D3S_CLRSIPOCOUNT, 3);
425
426 val = ((L0EN << tc->num_dsi_lanes) - L0EN) | DSI_CLEN_BIT;
427 d2l_write(tc->i2c, PPI_LANEENABLE, val);
428 d2l_write(tc->i2c, DSI_LANEENABLE, val);
429
430 d2l_write(tc->i2c, PPI_STARTPPI, PPI_START_FUNCTION);
431 d2l_write(tc->i2c, DSI_STARTDSI, DSI_RX_START);
432
433 val_lvcfg = LVCFG_LVEN_BIT;
434 if (tc->dual_link) {
435 link = 2;
436 val_lvcfg |= TC358775_LVCFG_LVDLINK(1);
437 val_lvcfg |= TC358775_LVCFG_PCLKDIV(DIVIDE_BY_6);
438 } else {
439 link = 1;
440 val_lvcfg |= TC358775_LVCFG_PCLKDIV(DIVIDE_BY_3);
441 }
442
443 bus_formats = connector->display_info.bus_formats[0];
444
445 switch (bus_formats) {
446 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
447 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
448 /* RGB888 */
449 bpc = 8;
450 val = TC358775_VPCTRL_OPXLFMT(1);
451 break;
452 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
453 /* RGB666 */
454 bpc = 6;
455 val |= TC358775_VPCTRL_MSF(1);
456 break;
> 457 default:
458 dev_warn(tc->dev,
459 "unsupported LVDS bus format 0x%04x, using JEIDA\n",
460 bus_formats);
461 break;
462 }
463
464 dsiclk = mode->crtc_clock * 3 * bpc / tc->num_dsi_lanes / 1000;
465 clkdiv = dsiclk / DIVIDE_BY_3 * link;
466 byteclk = dsiclk / 4;
467 t1 = hactive * (bpc * 3 / 8) / tc->num_dsi_lanes;
468 t2 = ((100000 / clkdiv)) * (hactive + hback_porch + hsync_len + hfront_porch) / 1000;
469 t3 = ((t2 * byteclk) / 100) - (hactive * (bpc * 3 / 8) /
470 tc->num_dsi_lanes);
471
472 vsdelay = (clkdiv * (t1 + t3) / byteclk) - hback_porch - hsync_len - hactive;
473
474 val |= TC358775_VPCTRL_VSDELAY(vsdelay);
475 d2l_write(tc->i2c, VPCTRL, val);
476
477 d2l_write(tc->i2c, HTIM1, htime1);
478 d2l_write(tc->i2c, VTIM1, vtime1);
479 d2l_write(tc->i2c, HTIM2, htime2);
480 d2l_write(tc->i2c, VTIM2, vtime2);
481
482 d2l_write(tc->i2c, VFUEN, VFUEN_EN);
483 d2l_write(tc->i2c, SYSRST, SYS_RST_LCD);
484 d2l_write(tc->i2c, LVPHY0, LV_PHY0_PRBS_ON(4) | LV_PHY0_ND(6));
485
486 switch (bus_formats) {
487 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
488 /*
489 * Default hardware register settings of tc358775 configured
490 * with MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA jeida-24 format
491 */
492 dev_dbg(tc->dev, "bus_formats JEIDA24: %04x\n", bus_formats);
493 break;
494 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
495 /* VESA-24*/
496 d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3));
497 d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R4, LVI_R7, LVI_R5, LVI_G0));
498 d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_G6, LVI_G7));
499 d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0));
500 d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_B6, LVI_B7, LVI_B1, LVI_B2));
501 d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0));
502 d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_R6));
503 dev_dbg(tc->dev, "bus_formats VESA: %04x\n", bus_formats);
504 break;
505 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
506 /* JEIDA-18*/
507 d2l_write(tc->i2c, LV_MX0003, LV_MX(LVI_R0, LVI_R1, LVI_R2, LVI_R3));
508 d2l_write(tc->i2c, LV_MX0407, LV_MX(LVI_R4, LVI_L0, LVI_R5, LVI_G0));
509 d2l_write(tc->i2c, LV_MX0811, LV_MX(LVI_G1, LVI_G2, LVI_L0, LVI_L0));
510 d2l_write(tc->i2c, LV_MX1215, LV_MX(LVI_G3, LVI_G4, LVI_G5, LVI_B0));
511 d2l_write(tc->i2c, LV_MX1619, LV_MX(LVI_L0, LVI_L0, LVI_B1, LVI_B2));
512 d2l_write(tc->i2c, LV_MX2023, LV_MX(LVI_B3, LVI_B4, LVI_B5, LVI_L0));
513 d2l_write(tc->i2c, LV_MX2427, LV_MX(LVI_HS, LVI_VS, LVI_DE, LVI_L0));
514 dev_dbg(tc->dev, "bus_formats JEIDA18: %04x\n", bus_formats);
515 break;
516 default:
517 dev_warn(tc->dev,
518 "unsupported LVDS bus format 0x%04x\n", bus_formats);
519 break;
520 }
521
522 d2l_write(tc->i2c, VFUEN, VFUEN_EN);
523 d2l_write(tc->i2c, LVCFG, val_lvcfg);
524 }
525
526 enum drm_mode_status
> 527 tc_mode_valid(struct drm_bridge *bridge,
528 const struct drm_display_info *info,
529 const struct drm_display_mode *mode)
530 {
531 struct tc_data *tc = bridge_to_tc(bridge);
532
533 /*
534 * Maximum pixel clock speed 135MHz for single-link
535 * 270MHz for dual-link
536 */
537 if ((mode->clock > 135000 && tc->dual_link) ||
538 (mode->clock > 270000 && tc->dual_link))
539 return MODE_CLOCK_HIGH;
540
541 return MODE_OK;
542 }
543
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
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