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Date:   Thu,  9 Jul 2020 14:57:06 -0500
From:   Eddie James <eajames@...ux.ibm.com>
To:     linux-clk@...r.kernel.org
Cc:     linux-kernel@...r.kernel.org, linux-aspeed@...ts.ozlabs.org,
        linux-mmc@...r.kernel.org, andrew@...id.au, joel@....id.au,
        ulf.hansson@...aro.org, adrian.hunter@...el.com, sboyd@...nel.org,
        mturquette@...libre.com, eajames@...ux.ibm.com
Subject: [PATCH 2/2] mmc: sdhci-of-aspeed: Fix clock divider calculation

When calculating the clock divider, start dividing at 2 instead of 1.
The divider is divided by two at the end of the calculation, so starting
at 1 may result in a divider of 0, which shouldn't happen.

Signed-off-by: Eddie James <eajames@...ux.ibm.com>
---
 drivers/mmc/host/sdhci-of-aspeed.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of-aspeed.c
index 56912e30c47e..a1bcc0f4ba9e 100644
--- a/drivers/mmc/host/sdhci-of-aspeed.c
+++ b/drivers/mmc/host/sdhci-of-aspeed.c
@@ -68,7 +68,7 @@ static void aspeed_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
 	if (WARN_ON(clock > host->max_clk))
 		clock = host->max_clk;
 
-	for (div = 1; div < 256; div *= 2) {
+	for (div = 2; div < 256; div *= 2) {
 		if ((parent / div) <= clock)
 			break;
 	}
-- 
2.24.0

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