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Message-ID: <1594638676.29621.1.camel@mtkswgap22>
Date: Mon, 13 Jul 2020 19:11:16 +0800
From: Hanks Chen <hanks.chen@...iatek.com>
To: Matthias Brugger <matthias.bgg@...il.com>
CC: Linus Walleij <linus.walleij@...aro.org>,
Rob Herring <robh+dt@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
"Stephen Boyd" <sboyd@...nel.org>,
Sean Wang <sean.wang@...nel.org>,
mtk01761 <wendell.lin@...iatek.com>,
Andy Teng <andy.teng@...iatek.com>,
<linux-gpio@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-mediatek@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <wsd_upstream@...iatek.com>,
CC Hwang <cc.hwang@...iatek.com>,
Loda Chou <loda.chou@...iatek.com>
Subject: Re: [PATCH v7 7/7] arm64: dts: add dts nodes for MT6779
On Fri, 2020-07-10 at 15:47 +0200, Matthias Brugger wrote:
>
> On 02/07/2020 14:57, Hanks Chen wrote:
> > this adds initial MT6779 dts settings for board support,
> > including cpu, gic, timer, ccf, pinctrl, uart, sysirq...etc.
> >
> > Signed-off-by: Hanks Chen <hanks.chen@...iatek.com>
> > ---
> > arch/arm64/boot/dts/mediatek/Makefile | 1 +
> > arch/arm64/boot/dts/mediatek/mt6779-evb.dts | 31 +++
> > arch/arm64/boot/dts/mediatek/mt6779.dtsi | 271 +++++++++++++++++++++++++++
> > 3 files changed, 303 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt6779-evb.dts
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt6779.dtsi
> >
> [...]
> > +
> > + uart2: serial@...04000 {
> > + compatible = "mediatek,mt6779-uart",
> > + "mediatek,mt6577-uart";
> > + reg = <0 0x11004000 0 0x400>;
> > + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART1>;
>
> I suppose that should be:
>
> clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART2>;
>
My fault, I'll fix the typo in next version.
Thanks!
Hanks
>
> Regards,
> Matthias
>
> > + clock-names = "baud", "bus";
> > + status = "disabled";
> > + };
> > +
> > + audio: clock-controller@...10000 {
> > + compatible = "mediatek,mt6779-audio", "syscon";
> > + reg = <0 0x11210000 0 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + mfgcfg: clock-controller@...bf000 {
> > + compatible = "mediatek,mt6779-mfgcfg", "syscon";
> > + reg = <0 0x13fbf000 0 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + mmsys: syscon@...00000 {
> > + compatible = "mediatek,mt6779-mmsys", "syscon";
> > + reg = <0 0x14000000 0 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + imgsys: clock-controller@...20000 {
> > + compatible = "mediatek,mt6779-imgsys", "syscon";
> > + reg = <0 0x15020000 0 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + vdecsys: clock-controller@...00000 {
> > + compatible = "mediatek,mt6779-vdecsys", "syscon";
> > + reg = <0 0x16000000 0 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + vencsys: clock-controller@...00000 {
> > + compatible = "mediatek,mt6779-vencsys", "syscon";
> > + reg = <0 0x17000000 0 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + camsys: clock-controller@...00000 {
> > + compatible = "mediatek,mt6779-camsys", "syscon";
> > + reg = <0 0x1a000000 0 0x10000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + ipesys: clock-controller@...00000 {
> > + compatible = "mediatek,mt6779-ipesys", "syscon";
> > + reg = <0 0x1b000000 0 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
> > + };
> > +};
> >
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