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Message-ID: <4fe97f63-e552-3b2f-803c-53894b196bfd@linux.intel.com>
Date:   Wed, 29 Jul 2020 09:08:38 -0500
From:   Pierre-Louis Bossart <pierre-louis.bossart@...ux.intel.com>
To:     Brent Lu <brent.lu@...el.com>, alsa-devel@...a-project.org
Cc:     Guennadi Liakhovetski <guennadi.liakhovetski@...ux.intel.com>,
        Cezary Rojewski <cezary.rojewski@...el.com>,
        Kai Vehmanen <kai.vehmanen@...ux.intel.com>,
        Kuninori Morimoto <kuninori.morimoto.gx@...esas.com>,
        linux-kernel@...r.kernel.org, Takashi Iwai <tiwai@...e.com>,
        Jie Yang <yang.jie@...ux.intel.com>,
        Liam Girdwood <liam.r.girdwood@...ux.intel.com>,
        Sam McNally <sammc@...omium.org>,
        Mark Brown <broonie@...nel.org>,
        Ranjani Sridharan <ranjani.sridharan@...ux.intel.com>,
        Yu-Hsuan Hsu <yuhsuan@...omium.org>,
        Daniel Stuart <daniel.stuart14@...il.com>,
        Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
        Damian van Soelen <dj.vsoelen@...il.com>
Subject: Re: [PATCH 2/2] ASoC: Intel: Add period size constraint on strago
 board



On 7/29/20 6:03 AM, Brent Lu wrote:
> From: Yu-Hsuan Hsu <yuhsuan@...omium.org>
> 
> The CRAS server does not set the period size in hw_param so ALSA will
> calculate a value for period size which is based on the buffer size
> and other parameters. The value may not always be aligned with Atom's
> dsp design so a constraint is added to make sure the board always has
> a good value.
> 
> Cyan uses chtmax98090 and others(banon, celes, edgar, kefka...) use
> rt5650.

Is this patch required if you've already constrained the period sizes 
for the platform driver in patch1?

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