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Message-ID: <DM6PR11MB36421D9A808D401416B72D2D97710@DM6PR11MB3642.namprd11.prod.outlook.com>
Date:   Thu, 30 Jul 2020 08:02:09 +0000
From:   "Lu, Brent" <brent.lu@...el.com>
To:     Pierre-Louis Bossart <pierre-louis.bossart@...ux.intel.com>,
        "alsa-devel@...a-project.org" <alsa-devel@...a-project.org>
CC:     Guennadi Liakhovetski <guennadi.liakhovetski@...ux.intel.com>,
        "Rojewski, Cezary" <cezary.rojewski@...el.com>,
        Kai Vehmanen <kai.vehmanen@...ux.intel.com>,
        Kuninori Morimoto <kuninori.morimoto.gx@...esas.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Takashi Iwai <tiwai@...e.com>,
        Jie Yang <yang.jie@...ux.intel.com>,
        Liam Girdwood <liam.r.girdwood@...ux.intel.com>,
        Sam McNally <sammc@...omium.org>,
        Mark Brown <broonie@...nel.org>,
        "Ranjani Sridharan" <ranjani.sridharan@...ux.intel.com>,
        Yu-Hsuan Hsu <yuhsuan@...omium.org>,
        Daniel Stuart <daniel.stuart14@...il.com>,
        "Andy Shevchenko" <andriy.shevchenko@...ux.intel.com>,
        Damian van Soelen <dj.vsoelen@...il.com>
Subject: RE: [PATCH 2/2] ASoC: Intel: Add period size constraint on strago
 board


> 
> Is this patch required if you've already constrained the period sizes for the
> platform driver in patch1?

Yes or alsa will select 320 as default period size for it.


Regards,
Brent

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