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Message-ID: <DM6PR11MB364247C4C6F5B310F3E1E652974E0@DM6PR11MB3642.namprd11.prod.outlook.com>
Date:   Fri, 31 Jul 2020 12:28:53 +0000
From:   "Lu, Brent" <brent.lu@...el.com>
To:     Takashi Iwai <tiwai@...e.de>,
        Pierre-Louis Bossart <pierre-louis.bossart@...ux.intel.com>
CC:     "alsa-devel@...a-project.org" <alsa-devel@...a-project.org>,
        "Guennadi Liakhovetski" <guennadi.liakhovetski@...ux.intel.com>,
        "Rojewski, Cezary" <cezary.rojewski@...el.com>,
        Kai Vehmanen <kai.vehmanen@...ux.intel.com>,
        Kuninori Morimoto <kuninori.morimoto.gx@...esas.com>,
        Jie Yang <yang.jie@...ux.intel.com>,
        Takashi Iwai <tiwai@...e.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Liam Girdwood <liam.r.girdwood@...ux.intel.com>,
        Sam McNally <sammc@...omium.org>,
        "Mark Brown" <broonie@...nel.org>,
        Ranjani Sridharan <ranjani.sridharan@...ux.intel.com>,
        Daniel Stuart <daniel.stuart14@...il.com>,
        Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
        Yu-Hsuan Hsu <yuhsuan@...omium.org>,
        Damian van Soelen <dj.vsoelen@...il.com>
Subject: RE: [PATCH 2/2] ASoC: Intel: Add period size constraint on strago
 board

> 
> If the 1ms alignment is the condition, it can be better with a different
> hw_params constraint.  We can use
> snd_pcm_hw_constraint_step() for such a purpose.
Will fix. Thanks.

Regards,
Brent
> 
> 
> thanks,
> 
> Takashi

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