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Message-ID: <CAAOTY_9aDqz3muo6ynqX9r0VjW7tD5vvZOiQyR8UZOTUct8oVA@mail.gmail.com>
Date: Tue, 4 Aug 2020 23:00:05 +0800
From: Chun-Kuang Hu <chunkuang.hu@...nel.org>
To: Frank Wunderlich <linux@...web.de>
Cc: "moderated list:ARM/Mediatek SoC support"
<linux-mediatek@...ts.infradead.org>,
Chun-Kuang Hu <chunkuang.hu@...nel.org>,
Ryder Lee <ryder.lee@...iatek.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
Frank Wunderlich <frank-w@...lic-files.de>,
David Airlie <airlied@...ux.ie>,
chunhui dai <chunhui.dai@...iatek.com>,
linux-kernel <linux-kernel@...r.kernel.org>,
DRI Development <dri-devel@...ts.freedesktop.org>,
CK Hu <ck.hu@...iatek.com>, Daniel Vetter <daniel@...ll.ch>,
Matthias Brugger <matthias.bgg@...il.com>,
Bibby Hsieh <bibby.hsieh@...iatek.com>,
Linux ARM <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v3 5/5] arm: dts: mt7623: add display subsystem related
device nodes
Hi, Frank:
Frank Wunderlich <linux@...web.de> 於 2020年8月4日 週二 下午7:00寫道：
>
> From: Ryder Lee <ryder.lee@...iatek.com>
>
> Add display subsystem related device nodes for MT7623.
>
> Cc: CK Hu <ck.hu@...iatek.com>
> Signed-off-by: chunhui dai <chunhui.dai@...iatek.com>
> Signed-off-by: Bibby Hsieh <bibby.hsieh@...iatek.com>
> Signed-off-by: Ryder Lee <ryder.lee@...iatek.com>
> Signed-off-by: Frank Wunderlich <frank-w@...lic-files.de>
> Tested-by: Frank Wunderlich <frank-w@...lic-files.de>
> ---
> changed v2->v3:
> drop bls to dpi routing
> ---
> arch/arm/boot/dts/mt7623.dtsi | 177 ++++++++++++++++++
> arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 72 +++++++
> arch/arm/boot/dts/mt7623n-rfb-emmc.dts | 72 +++++++
> 3 files changed, 321 insertions(+)
>
> diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
> index a106c0d90a52..d584a3d678ba 100644
> --- a/arch/arm/boot/dts/mt7623.dtsi
> +++ b/arch/arm/boot/dts/mt7623.dtsi
> @@ -24,6 +24,11 @@ / {
> #address-cells = <2>;
> #size-cells = <2>;
>
> + aliases {
> + rdma0 = &rdma0;
> + rdma1 = &rdma1;
> + };
> +
> cpu_opp_table: opp-table {
> compatible = "operating-points-v2";
> opp-shared;
> @@ -321,6 +326,25 @@ pwrap: pwrap@...0d000 {
> clock-names = "spi", "wrap";
> };
>
> + mipi_tx0: mipi-dphy@...10000 {
> + compatible = "mediatek,mt7623-mipi-tx",
In mediatek,dsi.txt [1], "mediatek,mt7623-mipi-tx" is undefined.
[1] https://www.kernel.org/doc/Documentation/devicetree/bindings/display/mediatek/mediatek%2Cdsi.txt
> + "mediatek,mt2701-mipi-tx";
> + reg = <0 0x10010000 0 0x90>;
> + clocks = <&clk26m>;
> + clock-output-names = "mipi_tx0_pll";
> + #clock-cells = <0>;
> + #phy-cells = <0>;
> + };
> +
> + cec: cec@...12000 {
> + compatible = "mediatek,mt7623-cec",
Please explicitly define "mediatek,mt7623-cec" in mediatek,hdmi.txt [2].
[2] https://www.kernel.org/doc/Documentation/devicetree/bindings/display/mediatek/mediatek%2Chdmi.txt
> + "mediatek,mt8173-cec";
> + reg = <0 0x10012000 0 0xbc>;
> + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&infracfg CLK_INFRA_CEC>;
> + status = "disabled";
> + };
> +
> cir: cir@...13000 {
> compatible = "mediatek,mt7623-cir";
> reg = <0 0x10013000 0 0x1000>;
> @@ -369,6 +393,18 @@ apmixedsys: syscon@...09000 {
> #clock-cells = <1>;
> };
>
> + hdmi_phy: phy@...09100 {
> + compatible = "mediatek,mt7623-hdmi-phy",
Ditto.
> + "mediatek,mt2701-hdmi-phy";
> + reg = <0 0x10209100 0 0x24>;
> + clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
> + clock-names = "pll_ref";
> + clock-output-names = "hdmitx_dig_cts";
> + #clock-cells = <0>;
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> +
> rng: rng@...0f000 {
> compatible = "mediatek,mt7623-rng";
> reg = <0 0x1020f000 0 0x1000>;
> @@ -568,6 +604,16 @@ bch: ecc@...0e000 {
> status = "disabled";
> };
>
> + hdmiddc0: i2c@...13000 {
> + compatible = "mediatek,mt7623-hdmi-ddc",
Ditto.
> + "mediatek,mt8173-hdmi-ddc";
> + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
> + reg = <0 0x11013000 0 0x1C>;
> + clocks = <&pericfg CLK_PERI_I2C3>;
> + clock-names = "ddc-i2c";
> + status = "disabled";
> + };
> +
> nor_flash: spi@...14000 {
> compatible = "mediatek,mt7623-nor",
> "mediatek,mt8173-nor";
> @@ -766,6 +812,84 @@ mmsys: syscon@...00000 {
> #clock-cells = <1>;
> };
>
> + display_components: dispsys@...00000 {
> + compatible = "mediatek,mt7623-mmsys",
> + "mediatek,mt2701-mmsys";
In mediatek,mmsys.txt [3], this should be:
mmsys: syscon@...00000 {
compatible = "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon"
[3] https://www.kernel.org/doc/Documentation/devicetree/bindings/arm/mediatek/mediatek%2Cmmsys.txt
> + reg = <0 0x14000000 0 0x1000>;
> + power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> + };
> +
> + ovl@...07000 {
> + compatible = "mediatek,mt7623-disp-ovl",
This is not defined in mediatek,disp.txt [4].
[4] https://www.kernel.org/doc/Documentation/devicetree/bindings/display/mediatek/mediatek%2Cdisp.txt
> + "mediatek,mt2701-disp-ovl";
> + reg = <0 0x14007000 0 0x1000>;
> + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&mmsys CLK_MM_DISP_OVL>;
> + iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>;
> + mediatek,larb = <&larb0>;
> + };
> +
> + rdma0: rdma@...08000 {
> + compatible = "mediatek,mt7623-disp-rdma",
> + "mediatek,mt2701-disp-rdma";
> + reg = <0 0x14008000 0 0x1000>;
> + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&mmsys CLK_MM_DISP_RDMA>;
> + iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>;
> + mediatek,larb = <&larb0>;
> + };
> +
> + wdma@...09000 {
> + compatible = "mediatek,mt7623-disp-wdma",
> + "mediatek,mt2701-disp-wdma";
> + reg = <0 0x14009000 0 0x1000>;
> + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&mmsys CLK_MM_DISP_WDMA>;
> + iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>;
> + mediatek,larb = <&larb0>;
> + };
> +
> + bls: pwm@...0a000 {
> + compatible = "mediatek,mt7623-disp-pwm",
> + "mediatek,mt2701-disp-pwm";
> + reg = <0 0x1400a000 0 0x1000>;
> + #pwm-cells = <2>;
> + clocks = <&mmsys CLK_MM_MDP_BLS_26M>,
> + <&mmsys CLK_MM_DISP_BLS>;
> + clock-names = "main", "mm";
> + status = "disabled";
> + };
> +
> + color@...0b000 {
> + compatible = "mediatek,mt7623-disp-color",
> + "mediatek,mt2701-disp-color";
> + reg = <0 0x1400b000 0 0x1000>;
> + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&mmsys CLK_MM_DISP_COLOR>;
> + };
> +
> + dsi: dsi@...0c000 {
> + compatible = "mediatek,mt7623-dsi",
This is not defined in mediatek,dsi.txt [1].
> + "mediatek,mt2701-dsi";
> + reg = <0 0x1400c000 0 0x1000>;
> + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&mmsys CLK_MM_DSI_ENGINE>,
> + <&mmsys CLK_MM_DSI_DIG>,
> + <&mipi_tx0>;
> + clock-names = "engine", "digital", "hs";
> + phys = <&mipi_tx0>;
> + phy-names = "dphy";
> + status = "disabled";
> + };
> +
> + mutex: mutex@...0e000 {
> + compatible = "mediatek,mt7623-disp-mutex",
> + "mediatek,mt2701-disp-mutex";
> + reg = <0 0x1400e000 0 0x1000>;
> + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&mmsys CLK_MM_MUTEX_32K>;
> + };
> +
> larb0: larb@...10000 {
> compatible = "mediatek,mt7623-smi-larb",
> "mediatek,mt2701-smi-larb";
> @@ -778,6 +902,44 @@ larb0: larb@...10000 {
> power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
> };
>
> + rdma1: rdma@...12000 {
> + compatible = "mediatek,mt7623-disp-rdma",
> + "mediatek,mt2701-disp-rdma";
> + reg = <0 0x14012000 0 0x1000>;
> + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&mmsys CLK_MM_DISP_RDMA1>;
> + iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>;
> + mediatek,larb = <&larb0>;
> + };
> +
> + dpi0: dpi@...14000 {
> + compatible = "mediatek,mt7623-dpi",
This is not defined in mediatek,dpi.txt [5].
[5] https://www.kernel.org/doc/Documentation/devicetree/bindings/display/mediatek/mediatek%2Cdpi.txt
Regards,
Chun-Kuang.
> + "mediatek,mt2701-dpi";
> + reg = <0 0x14014000 0 0x1000>;
> + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&mmsys CLK_MM_DPI1_DIGL>,
> + <&mmsys CLK_MM_DPI1_ENGINE>,
> + <&apmixedsys CLK_APMIXED_TVDPLL>;
> + clock-names = "pixel", "engine", "pll";
> + status = "disabled";
> + };
> +
> + hdmi0: hdmi@...15000 {
> + compatible = "mediatek,mt7623-hdmi",
> + "mediatek,mt8173-hdmi";
> + reg = <0 0x14015000 0 0x400>;
> + clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
> + <&mmsys CLK_MM_HDMI_PLL>,
> + <&mmsys CLK_MM_HDMI_AUDIO>,
> + <&mmsys CLK_MM_HDMI_SPDIF>;
> + clock-names = "pixel", "pll", "bclk", "spdif";
> + phys = <&hdmi_phy>;
> + phy-names = "hdmi";
> + mediatek,syscon-hdmi = <&mmsys 0x900>;
> + cec = <&cec>;
> + status = "disabled";
> + };
> +
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