linux-kernel - Re: [PATCH] MIPS: Provide Kconfig option for default IEEE754 conformance mode

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Message-ID: <alpine.LFD.2.21.2008051850390.24175@redsun52.ssa.fujisawa.hgst.com>
Date:   Wed, 5 Aug 2020 20:30:17 +0100 (BST)
From:   "Maciej W. Rozycki" <macro@....com>
To:     Jiaxun Yang <jiaxun.yang@...goat.com>
cc:     Serge Semin <Sergey.Semin@...kalelectronics.ru>,
        Serge Semin <fancer.lancer@...il.com>,
        linux-mips@...r.kernel.org,
        Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
        Paul Burton <paulburton@...nel.org>,
        Huacai Chen <chenhc@...ote.com>,
        Zhou Yanjie <zhouyanjie@...o.com>,
        周琰杰 (Zhou Yanjie) 
        <zhouyanjie@...yeetech.com>,
        Liangliang Huang <huanglllzu@...il.com>,
        linux-kernel@...r.kernel.org,
        "Maciej W. Rozycki" <macro@...ux-mips.org>
Subject: Re: [PATCH] MIPS: Provide Kconfig option for default IEEE754
 conformance mode

On Mon, 3 Aug 2020, Jiaxun Yang wrote:

> >   Well, originally plans were there to have NaN interlinking implemented
> > and no such mess or desire for hacks like one here would result.  Cf.:
> >
> > <https://gcc.gnu.org/ml/gcc/2015-11/msg00068.html>,
> > <https://gcc.gnu.org/ml/gcc/2016-05/msg00137.html>,
> >
> > and then:
> >
> > <https://lkml.org/lkml/2015/11/16/386>,
> > <https://sourceware.org/ml/libc-alpha/2015-11/msg00485.html>,
> > <https://sourceware.org/ml/binutils/2015-11/msg00170.html>,
> > <https://gcc.gnu.org/ml/gcc-patches/2015-11/msg03241.html>.
> >
> > You could well pick this work up and complete it if you like.  Final
> > conclusions for further work were made here:
> >
> > <https://gcc.gnu.org/ml/gcc/2016-11/msg00027.html>,
> > <https://gcc.gnu.org/ml/gcc/2017-08/msg00260.html>,
> > <https://gcc.gnu.org/ml/gcc/2017-10/msg00142.html>.
> >
> >   In the relaxed mode math programs may produce wrong results unless you
> > rebuild all your software for the correct NaN mode for the hardware used
> 
> Unfortunately most of the hardware guys didn't understood the difficulty 
> here.
> They decided to implement their hardware (P5600 & LS3A4000) as NaN2008 only.

 Sadly we (the software group) have lost the battle with the hardware 
group for the architecture to have FCSR.NAN2008 at least optionally 
writable, and the feature was subsequently removed from R5 on, along with 
the writability of FCSR.ABS2008 and the FCSR.MAC2008 bit altogether.

 Still R3 did permit those bits to be r/w (check rev. 3.50 of the 
architecture spec), which is why I implemented them as such in our FP 
emulation and also QEMU (although I need to note that a competing QEMU 
implementation was pushed upstream behind my back, which I believe wasn't 
as complete as mine, so this part may or may not have been implemented).

> I was thinking about let Kernel drop SIGFPE exception was caused by 
> mismatched NaN,
> as most applications don't rely on signaling NaN, but it is still a 
> dirty hack. Not a good
> idea in general.

 I think you cannot reliably send SIGFPE, because hardware does not trap 
on what it considers a qNaN.

 The interlinking effort was there to let individual pieces of software 
that have various requirements for NaNs, or do not use FP at all, to use a 
set of rules for possibly being allowed to run on incompatible hardware or 
loaded together by the dynamic loader.  For example there was a mode 
specified where all NaNs were silently treated as qNaNs regardless of the 
hardware interpretation of a specific encoding.

 I maintain this is the way to move forward, and if you are serious about 
keeping the architecture alive, then I strongly recommend to upstream the 
implementation, possibly based on my patches previously published, 
although as indicated in the discussion referred there have been design 
issues observed, which mean a certain amount of rework will be required, 
first on the spec, and then the implementation.

 FWIW,

  Maciej