linux-kernel - Re: [PATCH v2 00/17] arm/arm64: Turning IPIs into normal interrupts

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CAFA6WYNw7TgypuEdOVRQ4QzAe6BbOg8V0_6O-Xb1=8xybse=nQ@mail.gmail.com>
Date:   Tue, 11 Aug 2020 18:45:21 +0530
From:   Sumit Garg <sumit.garg@...aro.org>
To:     Marc Zyngier <maz@...nel.org>
Cc:     linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Will Deacon <will@...nel.org>,
        Catalin Marinas <catalin.marinas@....com>,
        Russell King <linux@....linux.org.uk>,
        Thomas Gleixner <tglx@...utronix.de>,
        Jason Cooper <jason@...edaemon.net>,
        Valentin Schneider <Valentin.Schneider@....com>,
        Florian Fainelli <f.fainelli@...il.com>,
        Gregory Clement <gregory.clement@...tlin.com>,
        Andrew Lunn <andrew@...n.ch>, kernel-team@...roid.com
Subject: Re: [PATCH v2 00/17] arm/arm64: Turning IPIs into normal interrupts

Hi Marc,

On Thu, 25 Jun 2020 at 01:28, Marc Zyngier <maz@...nel.org> wrote:
>
> For as long as SMP ARM has existed, IPIs have been handled as
> something special. The arch code and the interrupt controller exchange
> a couple of hooks (one to generate an IPI, another to handle it).
>
> Although this is perfectly manageable, it prevents the use of features
> that we could use if IPIs were Linux IRQs (such as pseudo-NMIs). It
> also means that each interrupt controller driver has to follow an
> architecture-specific interface instead of just implementing the base
> irqchip functionalities. The arch code also duplicates a number of
> things that the core irq code already does (such as calling
> set_irq_regs(), irq_enter()...).
>
> This series tries to remedy this on arm/arm64 by offering a new
> registration interface where the irqchip gives the arch code a range
> of interrupts to use for IPIs. The arch code requests these as normal
> per-cpu interrupts.
>
> The bulk of the work is at the interrupt controller level, where all 5
> irqchips used on arm+SMP/arm64 get converted.
>
> Finally, we drop the legacy registration interface as well as the
> custom statistics accounting.
>
> Note that I have had a look at providing a "generic" interface by
> expanding the kernel/irq/ipi.c bag of helpers, but so far all
> irqchips have very different requirements, so there is hardly anything
> to consolidate for now. Maybe some as hip04 and the Marvell horror get
> cleaned up (the latter certainly could do with a good dusting).
>
> This has been tested on a bunch of 32 and 64bit guests (GICv2, GICv3),
> as well as 64bit bare metal (GICv3). The RPi part has only been tested
> in QEMU as a 64bit guest, while the HiSi and Marvell parts have only
> been compile-tested.

This series works perfectly fine on Developerbox.

I just want to follow-up regarding when you are planning to push this
series upstream? Are you waiting for other irqchips (apart from GIC)
to be reviewed?

Actually mine work to turn IPI as a pseudo NMI [1] is dependent on
this patch-set.

[1] https://lkml.org/lkml/2020/5/20/488

-Sumit

>
> * From v1:
>   - Clarified the effect of nesting irq_enter/exit (Russell)
>   - Changed the point where we tear IPIs down on (Valentin)
>   - IPIs are no longer accessible from DT
>   - HIP04 and Armada 370-XP have been converted, but are untested
>   - arch-specific kstat accounting is removed
>   - ARM's legacy interface is dropped
>
> Marc Zyngier (17):
>   genirq: Add fasteoi IPI flow
>   genirq: Allow interrupts to be excluded from /proc/interrupts
>   arm64: Allow IPIs to be handled as normal interrupts
>   ARM: Allow IPIs to be handled as normal interrupts
>   irqchip/gic-v3: Describe the SGI range
>   irqchip/gic-v3: Configure SGIs as standard interrupts
>   irqchip/gic: Atomically update affinity
>   irqchip/gic: Refactor SMP configuration
>   irqchip/gic: Configure SGIs as standard interrupts
>   irqchip/gic-common: Don't enable SGIs by default
>   irqchip/bcm2836: Configure mailbox interrupts as standard interrupts
>   irqchip/hip04: Configure IPIs as standard interrupts
>   irqchip/armada-370-xp: Configure IPIs as standard interrupts
>   arm64: Kill __smp_cross_call and co
>   arm64: Remove custom IRQ stat accounting
>   ARM: Kill __smp_cross_call and co
>   ARM: Remove custom IRQ stat accounting
>
>  arch/arm/Kconfig                    |   1 +
>  arch/arm/include/asm/hardirq.h      |  17 --
>  arch/arm/include/asm/smp.h          |   5 +-
>  arch/arm/kernel/smp.c               | 135 +++++++++-----
>  arch/arm64/Kconfig                  |   1 +
>  arch/arm64/include/asm/hardirq.h    |   9 -
>  arch/arm64/include/asm/irq_work.h   |   4 +-
>  arch/arm64/include/asm/smp.h        |   6 +-
>  arch/arm64/kernel/smp.c             | 119 ++++++++-----
>  drivers/irqchip/irq-armada-370-xp.c | 262 +++++++++++++++++++---------
>  drivers/irqchip/irq-bcm2836.c       | 151 +++++++++++++---
>  drivers/irqchip/irq-gic-common.c    |   3 -
>  drivers/irqchip/irq-gic-v3.c        |  99 ++++++-----
>  drivers/irqchip/irq-gic.c           | 183 ++++++++++---------
>  drivers/irqchip/irq-hip04.c         |  89 +++++-----
>  include/linux/irq.h                 |   5 +-
>  kernel/irq/chip.c                   |  27 +++
>  kernel/irq/debugfs.c                |   1 +
>  kernel/irq/proc.c                   |   2 +-
>  kernel/irq/settings.h               |   7 +
>  20 files changed, 713 insertions(+), 413 deletions(-)
>
> --
> 2.27.0
>