linux-kernel - Re: [PATCH v2 00/17] arm/arm64: Turning IPIs into normal interrupts

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Date:   Tue, 11 Aug 2020 14:58:49 +0100
From:   Marc Zyngier <maz@...nel.org>
To:     Sumit Garg <sumit.garg@...aro.org>
Cc:     linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Will Deacon <will@...nel.org>,
        Catalin Marinas <catalin.marinas@....com>,
        Russell King <linux@....linux.org.uk>,
        Thomas Gleixner <tglx@...utronix.de>,
        Jason Cooper <jason@...edaemon.net>,
        Valentin Schneider <Valentin.Schneider@....com>,
        Florian Fainelli <f.fainelli@...il.com>,
        Gregory Clement <gregory.clement@...tlin.com>,
        Andrew Lunn <andrew@...n.ch>, kernel-team@...roid.com
Subject: Re: [PATCH v2 00/17] arm/arm64: Turning IPIs into normal interrupts

Hi Sumit,

On 2020-08-11 14:15, Sumit Garg wrote:
> Hi Marc,
> 
> On Thu, 25 Jun 2020 at 01:28, Marc Zyngier <maz@...nel.org> wrote:
>> 
>> For as long as SMP ARM has existed, IPIs have been handled as
>> something special. The arch code and the interrupt controller exchange
>> a couple of hooks (one to generate an IPI, another to handle it).
>> 
>> Although this is perfectly manageable, it prevents the use of features
>> that we could use if IPIs were Linux IRQs (such as pseudo-NMIs). It
>> also means that each interrupt controller driver has to follow an
>> architecture-specific interface instead of just implementing the base
>> irqchip functionalities. The arch code also duplicates a number of
>> things that the core irq code already does (such as calling
>> set_irq_regs(), irq_enter()...).
>> 
>> This series tries to remedy this on arm/arm64 by offering a new
>> registration interface where the irqchip gives the arch code a range
>> of interrupts to use for IPIs. The arch code requests these as normal
>> per-cpu interrupts.
>> 
>> The bulk of the work is at the interrupt controller level, where all 5
>> irqchips used on arm+SMP/arm64 get converted.
>> 
>> Finally, we drop the legacy registration interface as well as the
>> custom statistics accounting.
>> 
>> Note that I have had a look at providing a "generic" interface by
>> expanding the kernel/irq/ipi.c bag of helpers, but so far all
>> irqchips have very different requirements, so there is hardly anything
>> to consolidate for now. Maybe some as hip04 and the Marvell horror get
>> cleaned up (the latter certainly could do with a good dusting).
>> 
>> This has been tested on a bunch of 32 and 64bit guests (GICv2, GICv3),
>> as well as 64bit bare metal (GICv3). The RPi part has only been tested
>> in QEMU as a 64bit guest, while the HiSi and Marvell parts have only
>> been compile-tested.
> 
> This series works perfectly fine on Developerbox.
> 
> I just want to follow-up regarding when you are planning to push this
> series upstream? Are you waiting for other irqchips (apart from GIC)
> to be reviewed?

I'd certainly like people to review (and maybe test if they have
the HW at hand) the rest of the interrupt controller changes.

I'll probably repost the series around -rc1.

> Actually mine work to turn IPI as a pseudo NMI [1] is dependent on
> this patch-set.
> 
> [1] https://lkml.org/lkml/2020/5/20/488

I'm aware of this.

Thanks,

         M.
-- 
Jazz is not dead. It just smells funny...