lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Fri, 14 Aug 2020 12:04:05 +0200
From:   Nicolas Saenz Julienne <nsaenzjulienne@...e.de>
To:     Greg KH <gregkh@...uxfoundation.org>,
        Florian Fainelli <f.fainelli@...il.com>
Cc:     robh@...nel.org, wahrenst@....net, p.zabel@...gutronix.de,
        andy.shevchenko@...il.com, linux-usb@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-rpi-kernel@...ts.infradead.org,
        linux-arm-kernel@...ts.infradead.org,
        bcm-kernel-feedback-list@...adcom.com, tim.gover@...pberrypi.org,
        linux-pci@...r.kernel.org, helgaas@...nel.org,
        mathias.nyman@...ux.intel.com, lorenzo.pieralisi@....com
Subject: Re: [PATCH v5 0/9] Raspberry Pi 4 USB firmware initialization rework

On Fri, 2020-08-14 at 08:11 +0200, Greg KH wrote:
> On Thu, Aug 13, 2020 at 12:17:49PM -0700, Florian Fainelli wrote:
> > 
> > On 8/13/2020 3:01 AM, Nicolas Saenz Julienne wrote:
> > > Hi everyone.
> > > 
> > > On Mon, 2020-06-29 at 18:18 +0200, Nicolas Saenz Julienne wrote:
> > > > On the Raspberry Pi 4, after a PCI reset, VL805's firmware may either be
> > > > loaded directly from an EEPROM or, if not present, by the SoC's
> > > > co-processor, VideoCore. This series reworks how we handle this.
> > > > 
> > > > The previous solution makes use of PCI quirks and exporting platform
> > > > specific functions. Albeit functional it feels pretty shoehorned. This
> > > > proposes an alternative way of handling the triggering of the xHCI chip
> > > > initialization trough means of a reset controller.
> > > > 
> > > > The benefits are pretty evident: less platform churn in core xHCI code,
> > > > and no explicit device dependency management in pcie-brcmstb.
> > > > 
> > > > Note that patch #1 depends on another series[1], that was just applied
> > > > into the clk maintainer's tree.
> > > > 
> > > > The series is based on v5.8-rc3
> > > > 
> > > > v3: https://www.spinics.net/lists/arm-kernel/msg813612.html
> > > > v2: https://lkml.org/lkml/2020/6/9/875
> > > > v1: https://lore.kernel.org/linux-usb/20200608192701.18355-1-nsaenzjulienne@suse.de/T/#t
> > > > 
> > > > [1] https://lore.kernel.org/linux-clk/159304773261.62212.983376627029743900@swboyd.mtv.corp.google.com/T/#t
> > > > 
> > > > ---
> > > 
> > > We were waiting on a dependency to be merged upstream to get this. They are now
> > > in, so could we move things forward?
> > > 
> > > I can take the device tree patches, I guess philipp can take the reset
> > > controller code. But I'm not so sure who should be taking the PCI/USB
> > > counterparts.
> > 
> > Should we route everything through the USB tree since that is where the
> > changes that do require synchronization with other subsystems and DTS is
> > needed the most?
> > -- 
> > Florian
> 
> That's fine with me, if everyone else is ok with it :)

Sounds good to me.

Powered by blists - more mailing lists