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Message-ID: <CACna6ryhQ=pY0LgpgwbBo5WGXSSfserc3V1ELzD3WLgnTv3n+g@mail.gmail.com>
Date: Wed, 19 Aug 2020 17:36:03 +0200
From: Rafał Miłecki <zajec5@...il.com>
To: Florian Fainelli <f.fainelli@...il.com>
Cc: "linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
Christian Lamparter <chunkeey@...il.com>,
Hauke Mehrtens <hauke@...ke-m.de>,
"maintainer:BROADCOM BCM5301X ARM ARCHITECTURE"
<bcm-kernel-feedback-list@...adcom.com>,
Rob Herring <robh+dt@...nel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>,
open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] ARM: dts: BCM5301X: Fix pin controller node
On Wed, 19 Aug 2020 at 06:23, Florian Fainelli <f.fainelli@...il.com> wrote:
> The pin controller resources start at 0xc0 from the CRU base which is at
> 0x100 from th DMU base, for a final address of 0x1800_c1c0, whereas we
> are currently off by 0x100. The resource size of the CRU is also
> incorrect and should end at 0x248 bytes from 0x100 which is the start
> address. Finally, the compatibility strings defined for the
> pin-controller node should reflect the SoC being used.
>
> Fixes: 9994241ac97c ("ARM: dts: BCM5301X: Describe Northstar pins mux controller")
Let me verify that fix. I'm confused as I believe I got pinctrl
working for uart1 :|
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