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Date:   Sun, 23 Aug 2020 15:35:02 -0700
From:   Linus Torvalds <>
To:     Andy Lutomirski <>
Cc:     Thomas Gleixner <>,
        Linux Kernel Mailing List <>,
        "the arch/x86 maintainers" <>
Subject: Re: [GIT pull] x86/urgent for v5.9-rc2

On Sun, Aug 23, 2020 at 3:27 PM Andy Lutomirski <> wrote:
> Every interrupt is going to load the CS and SS descriptor cache lines.

Yeah, but this isn't even sharing the same GDT cache line. Those two
are at least in the same cacheline, and hey, that is forced upon us by
the architecture, so we don't have any choice.

But I guess this lsl thing only triggers on the paranoid entry, so
it's just NMI, DB and MCE.. Or?


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