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Date: Tue, 25 Aug 2020 16:38:17 +0530 From: Ravi Bangoria <ravi.bangoria@...ux.ibm.com> To: Christophe Leroy <christophe.leroy@...roup.eu>, christophe.leroy@....fr Cc: mpe@...erman.id.au, mikey@...ling.org, paulus@...ba.org, naveen.n.rao@...ux.vnet.ibm.com, pedromfc@...ux.ibm.com, rogealve@...ux.ibm.com, jniethe5@...il.com, linuxppc-dev@...ts.ozlabs.org, linux-kernel@...r.kernel.org, Ravi Bangoria <ravi.bangoria@...ux.ibm.com> Subject: Re: [PATCH v5 4/8] powerpc/watchpoint: Move DAWR detection logic outside of hw_breakpoint.c Hi Christophe, >> +static int cache_op_size(void) >> +{ >> +#ifdef __powerpc64__ >> + return ppc64_caches.l1d.block_size; >> +#else >> + return L1_CACHE_BYTES; >> +#endif >> +} > > You've got l1_dcache_bytes() in arch/powerpc/include/asm/cache.h to do that. > >> + >> +void wp_get_instr_detail(struct pt_regs *regs, struct ppc_inst *instr, >> + int *type, int *size, unsigned long *ea) >> +{ >> + struct instruction_op op; >> + >> + if (__get_user_instr_inatomic(*instr, (void __user *)regs->nip)) >> + return; >> + >> + analyse_instr(&op, regs, *instr); >> + *type = GETTYPE(op.type); >> + *ea = op.ea; >> +#ifdef __powerpc64__ >> + if (!(regs->msr & MSR_64BIT)) >> + *ea &= 0xffffffffUL; >> +#endif > > This #ifdef is unneeded, it should build fine on a 32 bits too. This patch is just a code movement from one file to another. I don't really change the logic. Would you mind if I do a separate patch for these changes (not a part of this series)? Thanks for review, Ravi
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