linux-kernel - Re: [PATCH v2 3/5] fpga manager: xilinx-spi: rework write

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <bc35f12e-6ff2-94a7-d519-94616f6dfc6c@lucaceresoli.net>
Date:   Thu, 27 Aug 2020 21:26:02 +0200
From:   Luca Ceresoli <luca@...aceresoli.net>
To:     Tom Rix <trix@...hat.com>, linux-fpga@...r.kernel.org
Cc:     Moritz Fischer <mdf@...nel.org>,
        Michal Simek <michal.simek@...inx.com>,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        Anatolij Gustschin <agust@...x.de>
Subject: Re: [PATCH v2 3/5] fpga manager: xilinx-spi: rework write_complete
 loop implementation

Hi Tom,

thanks for the prompt feedback!

On 27/08/20 20:59, Tom Rix wrote:
> 
> On 8/27/20 7:32 AM, Luca Ceresoli wrote:
>> In preparation to add error checking for gpiod_get_value(), rework
>> the loop to avoid the duplication of these lines:
>>
>> 	if (gpiod_get_value(conf->done))
>> 		return xilinx_spi_apply_cclk_cycles(conf);
>>
>> There is little advantage in this rework with current code. However
>> error checking will expand these two lines to five, making code
>> duplication more annoying.
>>
>> Signed-off-by: Luca Ceresoli <luca@...aceresoli.net>
>>
>> ---
>>
>> This patch is new in v2
>> ---
>>  drivers/fpga/xilinx-spi.c | 15 ++++++---------
>>  1 file changed, 6 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/fpga/xilinx-spi.c b/drivers/fpga/xilinx-spi.c
>> index 01f494172379..cfc933d70f52 100644
>> --- a/drivers/fpga/xilinx-spi.c
>> +++ b/drivers/fpga/xilinx-spi.c
>> @@ -151,22 +151,19 @@ static int xilinx_spi_write_complete(struct fpga_manager *mgr,
>>  				     struct fpga_image_info *info)
>>  {
>>  	struct xilinx_spi_conf *conf = mgr->priv;
>> -	unsigned long timeout;
>> +	unsigned long timeout = jiffies + usecs_to_jiffies(info->config_complete_timeout_us);
>>  	int ret;
>>  
>> -	if (gpiod_get_value(conf->done))
>> -		return xilinx_spi_apply_cclk_cycles(conf);
>> -
>> -	timeout = jiffies + usecs_to_jiffies(info->config_complete_timeout_us);
>> +	while (true) {
>> +		if (gpiod_get_value(conf->done))
>> +			return xilinx_spi_apply_cclk_cycles(conf);
>>  
>> -	while (time_before(jiffies, timeout)) {
>> +		if (time_after(jiffies, timeout))
>> +			break;
>>  
>>  		ret = xilinx_spi_apply_cclk_cycles(conf);
>>  		if (ret)
>>  			return ret;
>> -
>> -		if (gpiod_get_value(conf->done))
>> -			return xilinx_spi_apply_cclk_cycles(conf);
>>  	} 
> 
> Do you need another
> 
> 	if (gpiod_get_value(conf->done))
> 		return xilinx_spi_apply_cclk_cycles(conf);
> 
> here to cover the chance of sleeping in the loop ?

If I got your question correctly: if we get here it's because of a
timeout, thus programming has failed (DONE didn't come up after some
time), and checking it one more here seems pointless.

Does this reply your question?

-- 
Luca