linux-kernel - Re: [PATCH] MIPS: perf: Fix wrong check condition of Loongson event IDs

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Fri, 28 Aug 2020 16:49:37 +0800
From:   Huacai Chen <chenhc@...ote.com>
To:     Tiezhu Yang <yangtiezhu@...ngson.cn>,
        Pei Huang <huangpei@...ngson.cn>
Cc:     Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
        Jiaxun Yang <jiaxun.yang@...goat.com>,
        "open list:MIPS" <linux-mips@...r.kernel.org>,
        LKML <linux-kernel@...r.kernel.org>,
        Xuefeng Li <lixuefeng@...ngson.cn>
Subject: Re: [PATCH] MIPS: perf: Fix wrong check condition of Loongson event IDs

Hi, Pei,

On Thu, Aug 27, 2020 at 4:05 PM Tiezhu Yang <yangtiezhu@...ngson.cn> wrote:
>
> According to the user's manual chapter 8.2.1 of Loongson 3A2000 CPU [1]
> and 3A3000 CPU [2], we should take some event IDs such as 274, 358, 359
> and 360 as valid in the check condition, otherwise they are recognized
> as "not supported", fix it.
I think this patch needs you to confirm.

>
> [1] http://www.loongson.cn/uploadfile/cpu/3A2000/Loongson3A2000_user2.pdf
> [2] http://www.loongson.cn/uploadfile/cpu/3A3000/Loongson3A3000_3B3000user2.pdf
>
> Fixes: e9dfbaaeef1c ("MIPS: perf: Add hardware perf events support for new Loongson-3")
> Signed-off-by: Tiezhu Yang <yangtiezhu@...ngson.cn>
> ---
>  arch/mips/kernel/perf_event_mipsxx.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
> index efce5de..011eb6bb 100644
> --- a/arch/mips/kernel/perf_event_mipsxx.c
> +++ b/arch/mips/kernel/perf_event_mipsxx.c
> @@ -1898,8 +1898,8 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
>                                 (base_id >= 64 && base_id < 90) ||
>                                 (base_id >= 128 && base_id < 164) ||
>                                 (base_id >= 192 && base_id < 200) ||
> -                               (base_id >= 256 && base_id < 274) ||
> -                               (base_id >= 320 && base_id < 358) ||
> +                               (base_id >= 256 && base_id < 275) ||
> +                               (base_id >= 320 && base_id < 361) ||
>                                 (base_id >= 384 && base_id < 574))
>                                 break;
>
> --
> 2.1.0
>