[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <159881641150.20229.2207709091919187438.tip-bot2@tip-bot2>
Date: Sun, 30 Aug 2020 19:40:11 -0000
From: "tip-bot2 for Kyung Min Park" <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: Kyung Min Park <kyung.min.park@...el.com>,
Cathy Zhang <cathy.zhang@...el.com>,
Borislav Petkov <bp@...e.de>, Tony Luck <tony.luck@...el.com>,
x86 <x86@...nel.org>, LKML <linux-kernel@...r.kernel.org>
Subject: [tip: x86/cpu] x86/cpufeatures: Enumerate TSX suspend load address
tracking instructions
The following commit has been merged into the x86/cpu branch of tip:
Commit-ID: 18ec63faefb3fd311822556cd9b949f66b1eecee
Gitweb: https://git.kernel.org/tip/18ec63faefb3fd311822556cd9b949f66b1eecee
Author: Kyung Min Park <kyung.min.park@...el.com>
AuthorDate: Tue, 25 Aug 2020 08:47:57 +08:00
Committer: Borislav Petkov <bp@...e.de>
CommitterDate: Sun, 30 Aug 2020 17:43:40 +02:00
x86/cpufeatures: Enumerate TSX suspend load address tracking instructions
Intel TSX suspend load tracking instructions aim to give a way to choose
which memory accesses do not need to be tracked in the TSX read set. Add
TSX suspend load tracking CPUID feature flag TSXLDTRK for enumeration.
A processor supports Intel TSX suspend load address tracking if
CPUID.0x07.0x0:EDX[16] is present. Two instructions XSUSLDTRK, XRESLDTRK
are available when this feature is present.
The CPU feature flag is shown as "tsxldtrk" in /proc/cpuinfo.
Signed-off-by: Kyung Min Park <kyung.min.park@...el.com>
Signed-off-by: Cathy Zhang <cathy.zhang@...el.com>
Signed-off-by: Borislav Petkov <bp@...e.de>
Reviewed-by: Tony Luck <tony.luck@...el.com>
Link: https://lkml.kernel.org/r/1598316478-23337-2-git-send-email-cathy.zhang@intel.com
---
arch/x86/include/asm/cpufeatures.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 2901d5d..83fc9d3 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -368,6 +368,7 @@
#define X86_FEATURE_MD_CLEAR (18*32+10) /* VERW clears CPU buffers */
#define X86_FEATURE_TSX_FORCE_ABORT (18*32+13) /* "" TSX_FORCE_ABORT */
#define X86_FEATURE_SERIALIZE (18*32+14) /* SERIALIZE instruction */
+#define X86_FEATURE_TSXLDTRK (18*32+16) /* TSX Suspend Load Address Tracking */
#define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */
#define X86_FEATURE_ARCH_LBR (18*32+19) /* Intel ARCH LBR */
#define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
Powered by blists - more mailing lists