linux-kernel - Re: [PATCHv2] PCI: designware-ep: Fix the Header Type check

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Date:   Mon, 7 Sep 2020 10:28:41 +0100
From:   Lorenzo Pieralisi <lorenzo.pieralisi@....com>
To:     Zhiqiang Hou <Zhiqiang.Hou@....com>
Cc:     linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
        robh@...nel.org, bhelgaas@...gle.com, amurray@...goodpenguin.co.uk,
        jingoohan1@...il.com, gustavo.pimentel@...opsys.com
Subject: Re: [PATCHv2] PCI: designware-ep: Fix the Header Type check

On Tue, Aug 18, 2020 at 05:27:46PM +0800, Zhiqiang Hou wrote:
> From: Hou Zhiqiang <Zhiqiang.Hou@....com>
> 
> The current check will result in the multiple function device
> fails to initialize. So fix the check by masking out the
> multiple function bit.
> 
> Fixes: 0b24134f7888 ("PCI: dwc: Add validation that PCIe core is set to correct mode")
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@....com>
> ---
> V2:
>  - Add marco PCI_HEADER_TYPE_MASK and print the masked value.
> 
>  drivers/pci/controller/dwc/pcie-designware-ep.c | 3 ++-
>  include/uapi/linux/pci_regs.h                   | 1 +
>  2 files changed, 3 insertions(+), 1 deletion(-)

Applied to pci/dwc, thanks.

Lorenzo

> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 4680a51c49c0..0634bd3a0b96 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -653,7 +653,8 @@ int dw_pcie_ep_init_complete(struct dw_pcie_ep *ep)
>  	u32 reg;
>  	int i;
>  
> -	hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE);
> +	hdr_type = dw_pcie_readb_dbi(pci, PCI_HEADER_TYPE) &
> +		   PCI_HEADER_TYPE_MASK;
>  	if (hdr_type != PCI_HEADER_TYPE_NORMAL) {
>  		dev_err(pci->dev,
>  			"PCIe controller is not set to EP mode (hdr_type:0x%x)!\n",
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index f9701410d3b5..57a222014cd2 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -76,6 +76,7 @@
>  #define PCI_CACHE_LINE_SIZE	0x0c	/* 8 bits */
>  #define PCI_LATENCY_TIMER	0x0d	/* 8 bits */
>  #define PCI_HEADER_TYPE		0x0e	/* 8 bits */
> +#define  PCI_HEADER_TYPE_MASK		0x7f
>  #define  PCI_HEADER_TYPE_NORMAL		0
>  #define  PCI_HEADER_TYPE_BRIDGE		1
>  #define  PCI_HEADER_TYPE_CARDBUS	2
> -- 
> 2.17.1
>