lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Date:   Tue, 8 Sep 2020 17:39:27 -0500
From:   Bjorn Helgaas <helgaas@...nel.org>
To:     Hongtao Wu <wuht06@...il.com>
Cc:     Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Rob Herring <robh+dt@...nel.org>,
        Orson Zhai <orsonzhai@...il.com>,
        Baolin Wang <baolin.wang7@...il.com>,
        Chunyan Zhang <zhang.lyra@...il.com>,
        linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, Billows Wu <billows.wu@...soc.com>
Subject: Re: [PATCH v2 2/2] PCI: sprd: Add support for Unisoc SoCs' PCIe
 controller

On Tue, Sep 08, 2020 at 09:47:21PM +0800, Hongtao Wu wrote:
> From: Billows Wu <billows.wu@...soc.com>
> 
> This series adds PCIe controller driver for Unisoc SoCs.
> This controller is based on DesignWare PCIe IP.
> 
> Signed-off-by: Billows Wu <billows.wu@...soc.com>

Last signed-off must be from developer submitting the patch, i.e.,
Hongtao Wu; see https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst#n560

> +config PCIE_SPRD
> +	tristate "Unisoc PCIe controller - RC mode"

s/RC mode/Host mode/ to follow convention of other drivers.

> +	depends on ARCH_SPRD || COMPILE_TEST
> +	depends on PCI_MSI_IRQ_DOMAIN
> +	select PCIE_DW_HOST
> +	help
> +	  Unisoc PCIe controller uses the Designware core. It can be configured

s/Designware/DesignWare/

> +	  as an Endpoint (EP) or a Root complex (RC). In order to enable RC
> +	  mode, PCIE_SPRD must be selected.
> +	  Say Y or M here if you want to PCIe RC controller support on Unisoc
> +	  SoCs.

> +		dev_dbg(&pdev->dev,

dev_dbg(dev, ...

> +			"%2d:reg[0x%8x] mask[0x%8x] val[0x%8x] result[0x%8x]\n",
> +			i, reg, mask, val, tmp_val);

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ