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Message-Id: <c75e35c53ad8eb24a3f21f17f383d1f0177138a8.1599719352.git.greentime.hu@sifive.com>
Date: Thu, 10 Sep 2020 16:11:59 +0800
From: Greentime Hu <greentime.hu@...ive.com>
To: greentime.hu@...ive.com, linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org, aou@...s.berkeley.edu,
palmer@...belt.com, paul.walmsley@...ive.com
Cc: Guo Ren <guoren@...ux.alibaba.com>, Guo Ren <guoren@...nel.org>
Subject: [RFC PATCH v7 04/21] riscv: Add new csr defines related to vector extension
Follow the riscv vector spec to add new csr numbers.
[guoren@...ux.alibaba.com: first porting for new vector related csr]
Signed-off-by: Greentime Hu <greentime.hu@...ive.com>
Signed-off-by: Guo Ren <guoren@...ux.alibaba.com>
Acked-by: Guo Ren <guoren@...nel.org>
---
arch/riscv/include/asm/csr.h | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index cec462e198ce..0d4c89fb97b5 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -24,6 +24,12 @@
#define SR_FS_CLEAN _AC(0x00004000, UL)
#define SR_FS_DIRTY _AC(0x00006000, UL)
+#define SR_VS _AC(0x00000600, UL) /* Vector Status */
+#define SR_VS_OFF _AC(0x00000000, UL)
+#define SR_VS_INITIAL _AC(0x00000200, UL)
+#define SR_VS_CLEAN _AC(0x00000400, UL)
+#define SR_VS_DIRTY _AC(0x00000600, UL)
+
#define SR_XS _AC(0x00018000, UL) /* Extension Status */
#define SR_XS_OFF _AC(0x00000000, UL)
#define SR_XS_INITIAL _AC(0x00008000, UL)
@@ -31,9 +37,9 @@
#define SR_XS_DIRTY _AC(0x00018000, UL)
#ifndef CONFIG_64BIT
-#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */
+#define SR_SD _AC(0x80000000, UL) /* FS/VS/XS dirty */
#else
-#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */
+#define SR_SD _AC(0x8000000000000000, UL) /* FS/VS/XS dirty */
#endif
/* SATP flags */
@@ -111,6 +117,12 @@
#define CSR_PMPADDR0 0x3b0
#define CSR_MHARTID 0xf14
+#define CSR_VSTART 0x8
+#define CSR_VCSR 0xf
+#define CSR_VL 0xc20
+#define CSR_VTYPE 0xc21
+#define CSR_VLENB 0xc22
+
#ifdef CONFIG_RISCV_M_MODE
# define CSR_STATUS CSR_MSTATUS
# define CSR_IE CSR_MIE
--
2.28.0
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