lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Thu, 10 Sep 2020 16:12:01 +0800 From: Greentime Hu <greentime.hu@...ive.com> To: greentime.hu@...ive.com, linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org, aou@...s.berkeley.edu, palmer@...belt.com, paul.walmsley@...ive.com Cc: Guo Ren <guoren@...ux.alibaba.com> Subject: [RFC PATCH v7 06/21] riscv: Add has_vector/riscv_vsize to save vector features. This patch is used to detect vector support status of CPU and use riscv_vsize to save the size of all the vector registers. It assumes all harts has the same capabilities in SMP system. [guoren@...ux.alibaba.com: add has_vector checking] Signed-off-by: Greentime Hu <greentime.hu@...ive.com> Signed-off-by: Guo Ren <guoren@...ux.alibaba.com> --- arch/riscv/kernel/cpufeature.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index f11ada3fa906..4d4f78f6a5db 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -21,6 +21,10 @@ static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly; #ifdef CONFIG_FPU bool has_fpu __read_mostly; #endif +#ifdef CONFIG_VECTOR +bool has_vector __read_mostly; +unsigned long riscv_vsize __read_mostly; +#endif /** * riscv_isa_extension_base() - Get base extension word @@ -149,4 +153,12 @@ void riscv_fill_hwcap(void) if (elf_hwcap & (COMPAT_HWCAP_ISA_F | COMPAT_HWCAP_ISA_D)) has_fpu = true; #endif + +#ifdef CONFIG_VECTOR + if (elf_hwcap & COMPAT_HWCAP_ISA_V) { + has_vector = true; + /* There are 32 vector registers with vlenb length. */ + riscv_vsize = csr_read(CSR_VLENB) * 32; + } +#endif } -- 2.28.0
Powered by blists - more mailing lists