linux-kernel - [PATCH 7/7] dmaengine: at_xdmac: add AXI priority support and recommended settings

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Message-ID: <20200914140956.221432-8-eugen.hristev@microchip.com>
Date:   Mon, 14 Sep 2020 17:09:56 +0300
From:   Eugen Hristev <eugen.hristev@...rochip.com>
To:     <vkoul@...nel.org>, <robh+dt@...nel.org>,
        <tudor.ambarus@...rochip.com>, <ludovic.desroches@...rochip.com>
CC:     <dmaengine@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <nicolas.ferre@...rochip.com>,
        Eugen Hristev <eugen.hristev@...rochip.com>
Subject: [PATCH 7/7] dmaengine: at_xdmac: add AXI priority support and recommended settings

The sama7g5 version of the XDMAC supports priority configuration and
outstanding capabilities.
Add defines for the specific registers for this configuration, together
with recommended settings.
However the settings are very different if the XDMAC is a mem2mem or a
per2mem controller.
Thus, we need to differentiate according to device tree property.

Signed-off-by: Eugen Hristev <eugen.hristev@...rochip.com>
---
 drivers/dma/at_xdmac.c      | 25 +++++++++++++++++++++++++
 drivers/dma/at_xdmac_regs.h | 16 ++++++++++++++++
 2 files changed, 41 insertions(+)

diff --git a/drivers/dma/at_xdmac.c b/drivers/dma/at_xdmac.c
index 874484a4e79f..8ea5558e127d 100644
--- a/drivers/dma/at_xdmac.c
+++ b/drivers/dma/at_xdmac.c
@@ -57,6 +57,8 @@ struct at_xdmac_layout {
 	u8				chan_cc_reg_base;
 	/* Source/Destination Interface must be specified or not */
 	bool				sdif;
+	/* AXI queue priority configuration supported */
+	bool				axi_config;
 };
 
 /* ----- Channels ----- */
@@ -135,6 +137,7 @@ static struct at_xdmac_layout at_xdmac_sama5d4_layout = {
 	.gswf = 0x40,
 	.chan_cc_reg_base = 0x50,
 	.sdif = true,
+	.axi_config = false,
 };
 
 static struct at_xdmac_layout at_xdmac_sama7g5_layout = {
@@ -147,6 +150,7 @@ static struct at_xdmac_layout at_xdmac_sama7g5_layout = {
 	.gswf = 0x50,
 	.chan_cc_reg_base = 0x60,
 	.sdif = false,
+	.axi_config = true,
 };
 
 static inline void __iomem *at_xdmac_chan_reg_base(struct at_xdmac *atxdmac, unsigned int chan_nb)
@@ -1863,6 +1867,25 @@ static int atmel_xdmac_resume(struct device *dev)
 }
 #endif /* CONFIG_PM_SLEEP */
 
+static void at_xdmac_axi_config(struct platform_device *pdev)
+{
+	struct at_xdmac	*atxdmac = (struct at_xdmac *)platform_get_drvdata(pdev);
+	bool dev_m2m;
+
+	if (!atxdmac->layout->axi_config)
+		return; /* Not supported */
+
+	dev_m2m = of_property_read_bool(pdev->dev.of_node, "microchip,m2m");
+
+	if (dev_m2m) {
+		at_xdmac_write(atxdmac, AT_XDMAC_GCFG, AT_XDMAC_GCFG_M2M);
+		at_xdmac_write(atxdmac, AT_XDMAC_GWAC, AT_XDMAC_GWAC_M2M);
+	} else {
+		at_xdmac_write(atxdmac, AT_XDMAC_GCFG, AT_XDMAC_GCFG_P2M);
+		at_xdmac_write(atxdmac, AT_XDMAC_GWAC, AT_XDMAC_GWAC_P2M);
+	}
+}
+
 static int at_xdmac_probe(struct platform_device *pdev)
 {
 	struct at_xdmac	*atxdmac;
@@ -2008,6 +2031,8 @@ static int at_xdmac_probe(struct platform_device *pdev)
 	dev_info(&pdev->dev, "%d channels, mapped at 0x%p\n",
 		 nr_channels, atxdmac->regs);
 
+	at_xdmac_axi_config(pdev);
+
 	return 0;
 
 err_dma_unregister:
diff --git a/drivers/dma/at_xdmac_regs.h b/drivers/dma/at_xdmac_regs.h
index 7b4b4e24de70..e5a58f6194aa 100644
--- a/drivers/dma/at_xdmac_regs.h
+++ b/drivers/dma/at_xdmac_regs.h
@@ -14,7 +14,23 @@
 #define		AT_XDMAC_FIFO_SZ(i)	(((i) >> 5) & 0x7FF)		/* Number of Bytes */
 #define		AT_XDMAC_NB_REQ(i)	((((i) >> 16) & 0x3F) + 1)	/* Number of Peripheral Requests Minus One */
 #define AT_XDMAC_GCFG		0x04	/* Global Configuration Register */
+#define		AT_XDMAC_WRHP(i)	(((i) & 0xF) << 4)
+#define		AT_XDMAC_WRMP(i)	(((i) & 0xF) << 8)
+#define		AT_XDMAC_WRLP(i)	(((i) & 0xF) << 12)
+#define		AT_XDMAC_RDHP(i)	(((i) & 0xF) << 16)
+#define		AT_XDMAC_RDMP(i)	(((i) & 0xF) << 20)
+#define		AT_XDMAC_RDLP(i)	(((i) & 0xF) << 24)
+#define		AT_XDMAC_RDSG(i)	(((i) & 0xF) << 28)
+#define AT_XDMAC_GCFG_M2M	(AT_XDMAC_RDLP(0xF) | AT_XDMAC_WRLP(0xF))
+#define AT_XDMAC_GCFG_P2M	(AT_XDMAC_RDSG(0x1) | AT_XDMAC_RDHP(0x3) | \
+				AT_XDMAC_WRHP(0x5))
 #define AT_XDMAC_GWAC		0x08	/* Global Weighted Arbiter Configuration Register */
+#define		AT_XDMAC_PW0(i)		(((i) & 0xF) << 0)
+#define		AT_XDMAC_PW1(i)		(((i) & 0xF) << 4)
+#define		AT_XDMAC_PW2(i)		(((i) & 0xF) << 8)
+#define		AT_XDMAC_PW3(i)		(((i) & 0xF) << 12)
+#define AT_XDMAC_GWAC_M2M	0
+#define AT_XDMAC_GWAC_P2M	(AT_XDMAC_PW0(0xF) | AT_XDMAC_PW2(0xF))
 #define AT_XDMAC_GIE		0x0C	/* Global Interrupt Enable Register */
 #define AT_XDMAC_GID		0x10	/* Global Interrupt Disable Register */
 #define AT_XDMAC_GIM		0x14	/* Global Interrupt Mask Register */
-- 
2.25.1