linux-kernel - Re: [PATCH v6 1/8] powerpc/watchpoint: Fix quarword instruction handling on p10 predecessors

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <4522c423-c020-3abc-8db6-acdc2a095d21@linux.ibm.com>
Date:   Thu, 17 Sep 2020 10:25:24 -0300
From:   Rogerio Alves <rcardoso@...ux.ibm.com>
To:     Ravi Bangoria <ravi.bangoria@...ux.ibm.com>, mpe@...erman.id.au,
        christophe.leroy@....fr
Cc:     mikey@...ling.org, jniethe5@...il.com, pedromfc@...ux.ibm.com,
        linux-kernel@...r.kernel.org, paulus@...ba.org,
        rogealve@...ux.ibm.com, naveen.n.rao@...ux.vnet.ibm.com,
        linuxppc-dev@...ts.ozlabs.org
Subject: Re: [PATCH v6 1/8] powerpc/watchpoint: Fix quarword instruction
 handling on p10 predecessors



On 9/2/20 1:29 AM, Ravi Bangoria wrote:
> On p10 predecessors, watchpoint with quarword access is compared at
> quardword length. If the watch range is doubleword or less than that
> in a first half of quarword aligned 16 bytes, and if there is any
> unaligned quadword access which will access only the 2nd half, the
> handler should consider it as extraneous and emulate/single-step it
> before continuing.
> 
> Reported-by: Pedro Miraglia Franco de Carvalho <pedromfc@...ux.ibm.com>
> Fixes: 74c6881019b7 ("powerpc/watchpoint: Prepare handler to handle more than one watchpoint")
> Signed-off-by: Ravi Bangoria <ravi.bangoria@...ux.ibm.com>
Tested-by: Rogerio Alves <rcardoso@...ux.ibm.com>
> ---
>   arch/powerpc/include/asm/hw_breakpoint.h |  1 +
>   arch/powerpc/kernel/hw_breakpoint.c      | 12 ++++++++++--
>   2 files changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/powerpc/include/asm/hw_breakpoint.h b/arch/powerpc/include/asm/hw_breakpoint.h
> index db206a7f38e2..9b68eafebf43 100644
> --- a/arch/powerpc/include/asm/hw_breakpoint.h
> +++ b/arch/powerpc/include/asm/hw_breakpoint.h
> @@ -42,6 +42,7 @@ struct arch_hw_breakpoint {
>   #else
>   #define HW_BREAKPOINT_SIZE  0x8
>   #endif
> +#define HW_BREAKPOINT_SIZE_QUADWORD	0x10
>   
>   #define DABR_MAX_LEN	8
>   #define DAWR_MAX_LEN	512
> diff --git a/arch/powerpc/kernel/hw_breakpoint.c b/arch/powerpc/kernel/hw_breakpoint.c
> index 1f4a1efa0074..9f7df1c37233 100644
> --- a/arch/powerpc/kernel/hw_breakpoint.c
> +++ b/arch/powerpc/kernel/hw_breakpoint.c
> @@ -520,9 +520,17 @@ static bool ea_hw_range_overlaps(unsigned long ea, int size,
>   				 struct arch_hw_breakpoint *info)
>   {
>   	unsigned long hw_start_addr, hw_end_addr;
> +	unsigned long align_size = HW_BREAKPOINT_SIZE;
>   
> -	hw_start_addr = ALIGN_DOWN(info->address, HW_BREAKPOINT_SIZE);
> -	hw_end_addr = ALIGN(info->address + info->len, HW_BREAKPOINT_SIZE);
> +	/*
> +	 * On p10 predecessors, quadword is handle differently then
> +	 * other instructions.
> +	 */
> +	if (!cpu_has_feature(CPU_FTR_ARCH_31) && size == 16)
> +		align_size = HW_BREAKPOINT_SIZE_QUADWORD;
> +
> +	hw_start_addr = ALIGN_DOWN(info->address, align_size);
> +	hw_end_addr = ALIGN(info->address + info->len, align_size);
>   
>   	return ((ea < hw_end_addr) && (ea + size > hw_start_addr));
>   }
>