linux-kernel - Re: [PATCH v2] arm64: Enable PCI write-combine resources under sysfs

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CAMj1kXGy7vNHu9sTw7e69qwc6L2_BFYzUG++5UJdrWs+-173EA@mail.gmail.com>
Date:   Fri, 18 Sep 2020 14:56:57 +0300
From:   Ard Biesheuvel <ardb@...nel.org>
To:     Catalin Marinas <catalin.marinas@....com>
Cc:     Clint Sbisa <csbisa@...zon.com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Benjamin Herrenschmidt <benh@...nel.crashing.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Bjorn Helgaas <helgaas@...nel.org>,
        Jason Gunthorpe <jgg@...dia.com>,
        Will Deacon <will@...nel.org>,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v2] arm64: Enable PCI write-combine resources under sysfs

On Fri, 18 Sep 2020 at 14:08, Catalin Marinas <catalin.marinas@....com> wrote:
>
> On Fri, Sep 18, 2020 at 03:33:12AM +0000, Clint Sbisa wrote:
> > This change exposes write-combine mappings under sysfs for
> > prefetchable PCI resources on arm64.
> >
> > Originally, the usage of "write combine" here was driven by the x86
> > definition of write combine. This definition is specific to x86 and
> > does not generalize to other architectures. However, the usage of WC
> > has mutated to "write combine" semantics, which is implemented
> > differently on each arch.
> >
> > Generally, prefetchable BARs are accepted to allow speculative
> > accesses, write combining, and re-ordering-- from the PCI perspective,
> > this means there are no read side effects. (This contradicts the PCI
> > spec which allows prefetchable BARs to have read side effects, but
> > this definition is ill-advised as it is impossible to meet.) On x86,
> > prefetchable BARs are mapped as WC as originally defined (with some
> > conditionals on arch features). On arm64, WC is taken to mean normal
> > non-cacheable memory.
> >
> > In practice, write combine semantics are used to minimize write
> > operations. A common usage of this is minimizing PCI TLPs which can
> > significantly improve performance with PCI devices. In order to
> > provide the same benefits to userspace, we need to allow userspace to
> > map prefetchable BARs with write combine semantics. The resourceX_wc
> > mapping is used today by userspace programs and libraries.
> >
> > While this model is flawed as "write combine" is very ill-defined, it
> > is already used by multiple non-x86 archs to expose write combine
> > semantics to user space. We enable this on arm64 to give userspace on
> > arm64 an equivalent mechanism for utilizing write combining with PCI
> > devices.
> >
> > Cc: Benjamin Herrenschmidt <benh@...nel.crashing.org>
> > Cc: Bjorn Helgaas <helgaas@...nel.org>
> > Cc: Catalin Marinas <catalin.marinas@....com>
> > Cc: Jason Gunthorpe <jgg@...dia.com>
> > Cc: Lorenzo Pieralisi <lorenzo.pieralisi@....com>
> > Cc: Will Deacon <will@...nel.org>
> > Signed-off-by: Clint Sbisa <csbisa@...zon.com>
>
> Acked-by: Catalin Marinas <catalin.marinas@....com>
>

Acked-by: Ard Biesheuvel <ardb@...nel.org>