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Date: Wed, 23 Sep 2020 09:00:11 +0800 From: Icenowy Zheng <icenowy@...c.io> To: Rob Herring <robh+dt@...nel.org>, Maxime Ripard <mripard@...nel.org>, Chen-Yu Tsai <wens@...e.org> Cc: devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org, linux-sunxi@...glegroups.com, Icenowy Zheng <icenowy@...c.io> Subject: [PATCH 4/7] ARM: dts: sun8i: V3/V3s/S3/S3L: add pinctrl for 8-bit parallel CSI The CSI1 controller of V3/V3s/S3/S3L SoCs is used for parallel CSI. As we're going to add support for Pine64 SCC board, which uses 8-bit parallel CSI (and the MCLK output), add the pinctrl node of 8-bit CSI and MCLK to the DTSI file. Signed-off-by: Icenowy Zheng <icenowy@...c.io> --- arch/arm/boot/dts/sun8i-v3s.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index 3e079973672d..19fba1a9115b 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -312,6 +312,20 @@ pio: pinctrl@...0800 { interrupt-controller; #interrupt-cells = <3>; + /omit-if-no-ref/ + csi1_8bit_pins: csi1-8bit-pins { + pins = "PE0", "PE2", "PE3", "PE8", "PE9", + "PE10", "PE11", "PE12", "PE13", "PE14", + "PE15"; + function = "csi"; + }; + + /omit-if-no-ref/ + csi1_mclk_pin: csi1-mclk-pin { + pins = "PE1"; + function = "csi"; + }; + i2c0_pins: i2c0-pins { pins = "PB6", "PB7"; function = "i2c0"; -- 2.27.0
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