linux-kernel - Re: [PATCH 4/4] pinctrl: aspeed-g5: Fix LPC register offsets

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Message-ID: <CACRpkdbn9294JnddMsmGooCe7KCxMiGbuAZ+OAuLwPkZUYD10A@mail.gmail.com>
Date:   Tue, 29 Sep 2020 14:42:22 +0200
From:   Linus Walleij <linus.walleij@...aro.org>
To:     "Chia-Wei, Wang" <chiawei_wang@...eedtech.com>,
        Andrew Jeffery <andrew@...id.au>
Cc:     Rob Herring <robh+dt@...nel.org>, Joel Stanley <joel@....id.au>,
        Corey Minyard <minyard@....org>, haiyue.wang@...ux.intel.com,
        cyrilbur@...il.com, rlippert@...gle.com,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>,
        linux-aspeed <linux-aspeed@...ts.ozlabs.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        OpenBMC Maillist <openbmc@...ts.ozlabs.org>,
        Ryan Chen <ryan_chen@...eedtech.com>
Subject: Re: [PATCH 4/4] pinctrl: aspeed-g5: Fix LPC register offsets

On Fri, Sep 11, 2020 at 5:47 AM Chia-Wei, Wang
<chiawei_wang@...eedtech.com> wrote:

> The LPC register offsets are fixed to adapt to the LPC DTS change,
> where the LPC partitioning is removed.
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@...eedtech.com>

I can apply this one patch if I get a review from one of the
Aspeed pinctrl maintainer.

Andrew?

Yours,
Linus Walleij