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Message-ID: <74f6c812041970cb8f5e8c0da22fca92@kernel.org>
Date:   Tue, 29 Sep 2020 11:54:49 +0100
From:   Marc Zyngier <maz@...nel.org>
To:     ito-yuichi@...itsu.com
Cc:     sumit.garg@...aro.org, tglx@...utronix.de, jason@...edaemon.net,
        catalin.marinas@....com, will@...nel.org,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 0/2] Enable support IPI_CPU_CRASH_STOP to be pseudo-NMI

On 2020-09-29 06:50, ito-yuichi@...itsu.com wrote:
> Hi Marc

[...]

>> >> The patch has been tested on ThunderX.
>> 
>> Which ThunderX? TX2 (at least the incarnation I used in the past) 
>> wasn't able
>> to correctly deal with priorities.
> 
> I tried it with ThunderX CN8890.
> If you tell me steps to reproduce the problem of TX2, I will
> investigate it with TX as well.

PMR_EL1 reporting fantasy values, non-uniform priority support across
the interrupt classes, and generally prone to lockups. The original TX
is a very different machine though (TX 1 and 2 only share the engraving
of the manufacturer on the heat-spreader).

         M.
-- 
Jazz is not dead. It just smells funny...

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