linux-kernel - Re: [PATCH v2 0/5] PCI: dwc: improve msi handling

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Message-ID: <5f4947b18bf381615a37aa81c2242477@kernel.org>
Date:   Tue, 29 Sep 2020 19:12:57 +0100
From:   Marc Zyngier <maz@...nel.org>
To:     Jon Hunter <jonathanh@...dia.com>
Cc:     Jisheng Zhang <Jisheng.Zhang@...aptics.com>,
        Kunihiko Hayashi <hayashi.kunihiko@...ionext.com>,
        Neil Armstrong <narmstrong@...libre.com>,
        linux-pci@...r.kernel.org,
        Binghui Wang <wangbinghui@...ilicon.com>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        Masahiro Yamada <yamada.masahiro@...ionext.com>,
        Thierry Reding <thierry.reding@...il.com>,
        linux-arm-kernel@...s.com, Vidya Sagar <vidyas@...dia.com>,
        Fabio Estevam <festevam@...il.com>,
        Jerome Brunet <jbrunet@...libre.com>,
        Rob Herring <robh@...nel.org>,
        Jesper Nilsson <jesper.nilsson@...s.com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Kevin Hilman <khilman@...libre.com>,
        Pratyush Anand <pratyush.anand@...il.com>,
        linux-tegra@...r.kernel.org, Krzysztof Kozlowski <krzk@...nel.org>,
        Kishon Vijay Abraham I <kishon@...com>,
        Kukjin Kim <kgene@...nel.org>,
        NXP Linux Team <linux-imx@....com>,
        Xiaowei Song <songxiaowei@...ilicon.com>,
        Richard Zhu <hongxing.zhu@....com>,
        Martin Blumenstingl <martin.blumenstingl@...glemail.com>,
        linux-arm-msm@...r.kernel.org,
        Sascha Hauer <s.hauer@...gutronix.de>,
        Yue Wang <yue.wang@...ogic.com>,
        linux-samsung-soc@...r.kernel.org,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        linux-amlogic@...ts.infradead.org, linux-omap@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        Jingoo Han <jingoohan1@...il.com>,
        Andy Gross <agross@...nel.org>, linux-kernel@...r.kernel.org,
        Stanimir Varbanov <svarbanov@...sol.com>,
        Pengutronix Kernel Team <kernel@...gutronix.de>,
        Gustavo Pimentel <gustavo.pimentel@...opsys.com>,
        Shawn Guo <shawnguo@...nel.org>,
        Lucas Stach <l.stach@...gutronix.de>
Subject: Re: [PATCH v2 0/5] PCI: dwc: improve msi handling

On 2020-09-29 19:02, Jon Hunter wrote:
> On 29/09/2020 18:25, Marc Zyngier wrote:
>> On 2020-09-29 14:22, Jon Hunter wrote:
>>> Hi Jisheng,
>>> 
>>> On 29/09/2020 11:48, Jisheng Zhang wrote:
>>>> Hi Jon,
>>>> 
>>>> On Fri, 25 Sep 2020 09:53:45 +0100 Jon Hunter wrote:
>>>> 
>>>>> 
>>>>> On 24/09/2020 12:05, Jisheng Zhang wrote:
>>>>>> Improve the msi code:
>>>>>> 1. Add proper error handling.
>>>>>> 2. Move dw_pcie_msi_init() from each users to designware host to 
>>>>>> solve
>>>>>> msi page leakage in resume path.
>>>>> 
>>>>> Apologies if this is slightly off topic, but I have been meaning to 
>>>>> ask
>>>>> about MSIs and PCI. On Tegra194 which uses the DWC PCI driver,
>>>>> whenever we
>>>>> hotplug CPUs we see the following warnings ...
>>>>> 
>>>>>  [      79.068351] WARNING KERN IRQ70: set affinity failed(-22).
>>>>>  [      79.068362] WARNING KERN IRQ71: set affinity failed(-22).
>>>>> 
>>>> 
>>>> I tried to reproduce this issue on Synaptics SoC, but can't 
>>>> reproduce
>>>> it.
>>>> Per my understanding of the code in kernel/irq/cpuhotplug.c, this
>>>> warning
>>>> happened when we migrate irqs away from the offline cpu, this 
>>>> implicitly
>>>> implies that before this point the irq has bind to the offline cpu,
>>>> but how
>>>> could this happen given current dw_pci_msi_set_affinity() 
>>>> implementation
>>>> always return -EINVAL
>>> 
>>> By default the smp_affinity should be set so that all CPUs can be
>>> interrupted ...
>>> 
>>> $ cat /proc/irq/70/smp_affinity
>>> 0xff
>>> 
>>> In my case there are 8 CPUs and so 0xff implies that the interrupt 
>>> can
>>> be triggered on any of the 8 CPUs.
>>> 
>>> Do you see the set_affinity callback being called for the DWC irqchip 
>>> in
>>> migrate_one_irq()?
>> 
>> The problem is common to all MSI implementations that end up muxing
>> all the end-point MSIs into a single interrupt. With these systems,
>> you cannot set the affinity of individual MSIs (they don't target a
>> CPU, they target another interrupt... braindead). Only the mux
>> interrupt can have its affinity changed.
>> 
>> So returning -EINVAL is the right thing to do.
> 
> Right, so if that is the case, then surely there should be some way to
> avoid these warnings because they are not relevant?

I don't think there is a way to do this, because the core code
doesn't (and cannot) know the exact interrupt topology.

The only alternative would be to change the affinity of the mux
interrupt when a MSI affinity changes, but that tends to break
userspace (irqbalance, for example).

         M.
-- 
Jazz is not dead. It just smells funny...