linux-kernel - Re: [PATCH 4/4] pinctrl: aspeed-g5: Fix LPC register offsets

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Message-Id: <3755eb41-e939-41b4-93ff-7bfcbdbc9f5b@www.fastmail.com>
Date:   Thu, 01 Oct 2020 10:12:30 +0930
From:   "Andrew Jeffery" <andrew@...id.au>
To:     "Linus Walleij" <linus.walleij@...aro.org>,
        "Chia-Wei, Wang" <chiawei_wang@...eedtech.com>
Cc:     "Rob Herring" <robh+dt@...nel.org>,
        "Joel Stanley" <joel@....id.au>, "Corey Minyard" <minyard@....org>,
        "Haiyue Wang" <haiyue.wang@...ux.intel.com>,
        "Cyril Bur" <cyrilbur@...il.com>,
        "Robert Lippert" <rlippert@...gle.com>,
        "Linux ARM" <linux-arm-kernel@...ts.infradead.org>,
        linux-aspeed <linux-aspeed@...ts.ozlabs.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "OpenBMC Maillist" <openbmc@...ts.ozlabs.org>,
        "Ryan Chen" <ryan_chen@...eedtech.com>
Subject: Re: [PATCH 4/4] pinctrl: aspeed-g5: Fix LPC register offsets



On Tue, 29 Sep 2020, at 22:12, Linus Walleij wrote:
> On Fri, Sep 11, 2020 at 5:47 AM Chia-Wei, Wang
> <chiawei_wang@...eedtech.com> wrote:
> 
> > The LPC register offsets are fixed to adapt to the LPC DTS change,
> > where the LPC partitioning is removed.
> >
> > Signed-off-by: Chia-Wei, Wang <chiawei_wang@...eedtech.com>
> 
> I can apply this one patch if I get a review from one of the
> Aspeed pinctrl maintainer.
> 
> Andrew?

There needs to be a v2 of the series that fixes the binding documentation, 
which will drive some discussion about backwards compatibility. So lets not 
apply this patch just yet.

Thanks for touching base!

Andrew