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Message-ID: <HK0PR06MB37793A5D2B57972AFFFBAA0E91330@HK0PR06MB3779.apcprd06.prod.outlook.com>
Date:   Wed, 30 Sep 2020 07:54:30 +0000
From:   ChiaWei Wang <chiawei_wang@...eedtech.com>
To:     Andrew Jeffery <andrew@...id.au>,
        Ryan Chen <ryan_chen@...eedtech.com>,
        Joel Stanley <joel@....id.au>
CC:     Robert Lippert <rlippert@...gle.com>,
        linux-aspeed <linux-aspeed@...ts.ozlabs.org>,
        Corey Minyard <minyard@....org>,
        Linus Walleij <linus.walleij@...aro.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        OpenBMC Maillist <openbmc@...ts.ozlabs.org>,
        Rob Herring <robh+dt@...nel.org>,
        Linux ARM <linux-arm-kernel@...ts.infradead.org>,
        Cyril Bur <cyrilbur@...il.com>,
        Haiyue Wang <haiyue.wang@...ux.intel.com>
Subject: RE: [PATCH 0/4] Remove LPC register partitioning

Hi Andrew,

> -----Original Message-----
> From: Andrew Jeffery <andrew@...id.au>
> Sent: Wednesday, September 30, 2020 2:12 PM
> To: Ryan Chen <ryan_chen@...eedtech.com>; ChiaWei Wang
> <chiawei_wang@...eedtech.com>; Joel Stanley <joel@....id.au>
> Subject: Re: [PATCH 0/4] Remove LPC register partitioning
> 
> 
> 
> On Mon, 28 Sep 2020, at 17:13, Ryan Chen wrote:
> > Hello Joel & Andrew,
> > 	Those patches are more organize for ASPEED SOC LPC register layout.
> > 	Does those patches have any feedback?
> 
> I support getting the problem fixed. However, the series also needs to fix the
> LPC devicetree binding at
> 
> Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> 
> What's proposed isn't backwards compatible. We need to agree that a
> breaking change is the way we want to go and get Rob's buy-in. Given the
> impact of the change I'd prefer we don't try to maintain backwards
> compatibility. All known users of the binding ship the dtb with the kernel.
> 
> Can we get a v2 with the binding documentation fixed? That will probably need
> some review.
Yes, I will fix the binding documentation and resend the v2 patch for the review.
Thanks.

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