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Message-ID: <1601719607.774.1.camel@mtkswgap22>
Date: Sat, 3 Oct 2020 18:06:47 +0800
From: Hanks Chen <hanks.chen@...iatek.com>
To: Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>
CC: Matthias Brugger <matthias.bgg@...il.com>,
<devicetree@...r.kernel.org>, CC Hwang <cc.hwang@...iatek.com>,
Andy Teng <andy.teng@...iatek.com>,
"Linus Walleij" <linus.walleij@...aro.org>,
YueHaibing <yuehaibing@...wei.com>,
<linux-kernel@...r.kernel.org>, <linux-clk@...r.kernel.org>,
<linux-gpio@...r.kernel.org>, Rob Herring <robh+dt@...nel.org>,
<linux-mediatek@...ts.infradead.org>,
Loda Chou <loda.chou@...iatek.com>,
mtk01761 <wendell.lin@...iatek.com>,
<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v10 3/3] clk: mediatek: add UART0 clock support
Hi Michael & Stephen,
Please kindly let me know your comments about this patch.
Thanks
Regards,
Hanks
On Tue, 2020-09-08 at 14:25 +0800, Hanks Chen wrote:
> Hi all,
>
> Gentle ping on this patch.
>
> Thanks
>
>
> Hanks Chen
>
>
> On Thu, 2020-07-30 at 21:30 +0800, Hanks Chen wrote:
> > Add MT6779 UART0 clock support.
> >
> > Fixes: 710774e04861 ("clk: mediatek: Add MT6779 clock support")
> > Signed-off-by: Wendell Lin <wendell.lin@...iatek.com>
> > Signed-off-by: Hanks Chen <hanks.chen@...iatek.com>
> > Reviewed-by: Matthias Brugger <matthias.bgg@...il.com>
> > ---
> > drivers/clk/mediatek/clk-mt6779.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c
> > index 9766cccf5844..6e0d3a166729 100644
> > --- a/drivers/clk/mediatek/clk-mt6779.c
> > +++ b/drivers/clk/mediatek/clk-mt6779.c
> > @@ -919,6 +919,8 @@ static const struct mtk_gate infra_clks[] = {
> > "pwm_sel", 19),
> > GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
> > "pwm_sel", 21),
> > + GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
> > + "uart_sel", 22),
> > GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
> > "uart_sel", 23),
> > GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",
>
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