linux-kernel - Re: [PATCH 3/5] x86/ioapic: Handle Extended Destination ID field in RTE

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Date:   Thu, 08 Oct 2020 13:41:51 +0200
From:   Thomas Gleixner <tglx@...utronix.de>
To:     David Woodhouse <dwmw2@...radead.org>, x86@...nel.org
Cc:     kvm <kvm@...r.kernel.org>, Paolo Bonzini <pbonzini@...hat.com>,
        linux-kernel <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 3/5] x86/ioapic: Handle Extended Destination ID field in RTE

On Wed, Oct 07 2020 at 13:20, David Woodhouse wrote:
> From: David Woodhouse <dwmw@...zon.co.uk>
>
> The IOAPIC Redirection Table Entries contain an 8-bit Extended
> Destination ID field which maps to bits 11-4 of the MSI address.
>
> The lowest bit is used to indicate remappable format, when interrupt
> remapping is in use. A hypervisor can use the other 7 bits to permit
> guests to address up to 15 bits of APIC IDs, thus allowing 32768 vCPUs
> before having to expose a vIOMMU and interrupt remapping to the guest.
>
> No behavioural change in this patch, since nothing yet permits APIC IDs
> above 255 to be used with the non-IR IOAPIC domain. Except for the case
> where IR is enabled but there are IOAPICs which aren't in the scope of
> any IOMMU, which is totally hosed anyway and needs fixing independently
> of this change.

Again: IOAPICs which are not covered by IR are detected and prevent IR
enablement which makes the above a fairy tale. Changelogs are about
facts.

> diff --git a/arch/x86/include/asm/io_apic.h b/arch/x86/include/asm/io_apic.h
> index a1a26f6d3aa4..e65a0b7379d0 100644
> --- a/arch/x86/include/asm/io_apic.h
> +++ b/arch/x86/include/asm/io_apic.h
> @@ -78,7 +78,8 @@ struct IO_APIC_route_entry {
>  		mask		:  1,	/* 0: enabled, 1: disabled */
>  		__reserved_2	: 15;
>  
> -	__u32	__reserved_3	: 24,
> +	__u32	__reserved_3	: 17,
> +		ext_dest	:  7,

This wants to be explicitely named 'virt_ext_dest'.

Thanks,

        tglx