linux-kernel - Re: [PATCH v3 11/18] dmaengine: idxd: ims setup for the vdcm

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20201009124945.GJ4734@nvidia.com>
Date:   Fri, 9 Oct 2020 09:49:45 -0300
From:   Jason Gunthorpe <jgg@...dia.com>
To:     "Raj, Ashok" <ashok.raj@...el.com>
CC:     Thomas Gleixner <tglx@...utronix.de>,
        Dave Jiang <dave.jiang@...el.com>, <vkoul@...nel.org>,
        <megha.dey@...el.com>, <maz@...nel.org>, <bhelgaas@...gle.com>,
        <alex.williamson@...hat.com>, <jacob.jun.pan@...el.com>,
        <yi.l.liu@...el.com>, <baolu.lu@...el.com>, <kevin.tian@...el.com>,
        <sanjay.k.kumar@...el.com>, <tony.luck@...el.com>,
        <jing.lin@...el.com>, <dan.j.williams@...el.com>,
        <kwankhede@...dia.com>, <eric.auger@...hat.com>,
        <parav@...lanox.com>, <rafael@...nel.org>, <netanelg@...lanox.com>,
        <shahafs@...lanox.com>, <yan.y.zhao@...ux.intel.com>,
        <pbonzini@...hat.com>, <samuel.ortiz@...el.com>,
        <mona.hossain@...el.com>, <dmaengine@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <x86@...nel.org>,
        <linux-pci@...r.kernel.org>, <kvm@...r.kernel.org>
Subject: Re: [PATCH v3 11/18] dmaengine: idxd: ims setup for the vdcm

On Fri, Oct 09, 2020 at 05:43:07AM -0700, Raj, Ashok wrote:
> On Fri, Oct 09, 2020 at 08:57:37AM -0300, Jason Gunthorpe wrote:
> > On Thu, Oct 08, 2020 at 06:22:31PM -0700, Raj, Ashok wrote:
> > 
> > > Not randomly put there Jason :-).. There is a good reason for it. 
> > 
> > Sure the PASID value being associated with the IRQ make sense, but
> > combining that register with the interrupt mask is just a compltely
> > random thing to do.
> 
> Hummm... Not sure what you are complaining.. but in any case giving
> hardware a more efficient way to store interrupt entries breaking any
> boundaries that maybe implied by the spec is why IMS was defined.

I'm saying this PASID stuff is just some HW detail of IDXD and nothing
that the core irqchip code should concern itself with

Jason