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Message-ID: <20201009124307.GA63643@otc-nc-03>
Date: Fri, 9 Oct 2020 05:43:07 -0700
From: "Raj, Ashok" <ashok.raj@...el.com>
To: Jason Gunthorpe <jgg@...dia.com>
Cc: Thomas Gleixner <tglx@...utronix.de>,
Dave Jiang <dave.jiang@...el.com>, vkoul@...nel.org,
megha.dey@...el.com, maz@...nel.org, bhelgaas@...gle.com,
alex.williamson@...hat.com, jacob.jun.pan@...el.com,
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netanelg@...lanox.com, shahafs@...lanox.com,
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dmaengine@...r.kernel.org, linux-kernel@...r.kernel.org,
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Ashok Raj <ashok.raj@...el.com>
Subject: Re: [PATCH v3 11/18] dmaengine: idxd: ims setup for the vdcm
On Fri, Oct 09, 2020 at 08:57:37AM -0300, Jason Gunthorpe wrote:
> On Thu, Oct 08, 2020 at 06:22:31PM -0700, Raj, Ashok wrote:
>
> > Not randomly put there Jason :-).. There is a good reason for it.
>
> Sure the PASID value being associated with the IRQ make sense, but
> combining that register with the interrupt mask is just a compltely
> random thing to do.
Hummm... Not sure what you are complaining.. but in any case giving
hardware a more efficient way to store interrupt entries breaking any
boundaries that maybe implied by the spec is why IMS was defined.
>
> If this HW was using MSI-X PASID would have been given its own
> register.
Well there is no MSI-X PASID is there?
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