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Message-ID: <20201009115737.GI4734@nvidia.com>
Date: Fri, 9 Oct 2020 08:57:37 -0300
From: Jason Gunthorpe <jgg@...dia.com>
To: "Raj, Ashok" <ashok.raj@...el.com>
CC: Thomas Gleixner <tglx@...utronix.de>,
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Subject: Re: [PATCH v3 11/18] dmaengine: idxd: ims setup for the vdcm
On Thu, Oct 08, 2020 at 06:22:31PM -0700, Raj, Ashok wrote:
> Not randomly put there Jason :-).. There is a good reason for it.
Sure the PASID value being associated with the IRQ make sense, but
combining that register with the interrupt mask is just a compltely
random thing to do.
If this HW was using MSI-X PASID would have been given its own
register.
Jason
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