linux-kernel - Re: [PATCH 1/1] clk: aspeed: modify some default clks are critical

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Message-ID: <160264382296.310579.9835482254268204873@swboyd.mtv.corp.google.com>
Date:   Tue, 13 Oct 2020 19:50:22 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     Andrew Jeffery <andrew@...id.au>, Joel Stanley <joel@....id.au>,
        Michael Turquette <mturquette@...libre.com>,
        Ryan Chen <ryan_chen@...eedtech.com>, bmc-sw@...eedtech.com,
        linux-arm-kernel@...ts.infradead.org,
        linux-aspeed@...ts.ozlabs.org, linux-clk@...r.kernel.org,
        linux-kernel@...r.kernel.org
Cc:     Ryan Chen <ryan_chen@...eedtech.com>
Subject: Re: [PATCH 1/1] clk: aspeed: modify some default clks are critical

Quoting Ryan Chen (2020-09-28 00:01:08)
> In ASPEED SoC LCLK is LPC clock for all SuperIO device, UART1/UART2 are
> default for Host SuperIO UART device, eSPI clk for Host eSPI bus access
> eSPI slave channel, those clks can't be disable should keep default,
> otherwise will affect Host side access SuperIO and SPI slave device.
> 
> Signed-off-by: Ryan Chen <ryan_chen@...eedtech.com>
> ---

Is there resolution on this thread?