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Date:   Tue, 13 Oct 2020 19:45:48 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     Alexandru Ardelean <alexandru.ardelean@...log.com>,
        linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org
Cc:     lars@...afoo.de, mturquette@...libre.com, mdf@...nel.org,
        Alexandru Ardelean <alexandru.ardelean@...log.com>
Subject: Re: [PATCH 1/2] clk: axi-clkgen: Add support for fractional dividers

Quoting Alexandru Ardelean (2020-10-01 01:59:47)
> From: Lars-Peter Clausen <lars@...afoo.de>
> 
> The axi-clkgen has (optional) fractional dividers on the output clock
> divider and feedback clock divider path. Utilizing the fractional dividers
> allows for a better resolution of the output clock, being able to
> synthesize more frequencies.
> 
> Rework the driver support to support the fractional register fields, both
> for setting a new rate as well as reading back the current rate from the
> hardware.
> 
> For setting the rate if no perfect divider settings were found in
> non-fractional mode try again in fractional mode and see if better settings
> can be found. This appears to be the recommended mode of operation.
> 
> Signed-off-by: Lars-Peter Clausen <lars@...afoo.de>
> Signed-off-by: Alexandru Ardelean <alexandru.ardelean@...log.com>
> ---

Applied to clk-next

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