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Message-ID: <20201015065532.GA15371@infradead.org>
Date: Thu, 15 Oct 2020 07:55:32 +0100
From: Christoph Hellwig <hch@...radead.org>
To: Robin Murphy <robin.murphy@....com>
Cc: Christoph Hellwig <hch@...radead.org>,
Jonathan Marek <jonathan@...ek.ca>,
David Airlie <airlied@...ux.ie>,
freedreno@...ts.freedesktop.org,
open list <linux-kernel@...r.kernel.org>,
"open list:DRM DRIVER FOR MSM ADRENO GPU"
<dri-devel@...ts.freedesktop.org>,
iommu@...ts.linux-foundation.org, Daniel Vetter <daniel@...ll.ch>,
"open list:DRM DRIVER FOR MSM ADRENO GPU"
<linux-arm-msm@...r.kernel.org>, Sean Paul <sean@...rly.run>
Subject: Re: [PATCH 2/3] drm/msm: add DRM_MSM_GEM_SYNC_CACHE for non-coherent
cache maintenance
On Tue, Oct 13, 2020 at 02:42:38PM +0100, Robin Murphy wrote:
> I still think this situation would be best handled with a variant of
> dma_ops_bypass that also guarantees to bypass SWIOTLB, and can be set
> automatically when attaching to an unmanaged IOMMU domain.
dma_ops_bypass should mostly do the right thing as-is. swiotlb bouncing
is triggered of two things:
1) the dma_mask. This is under control of the driver, and obviously
if it is too small for a legit reason we can't just proceed
2) force_dma_unencrypted() - we'd need to do an opt-out here, either
by a flag or by being smart and looking for an attached iommu on
the device
> That way the
> device driver can make DMA API calls in the appropriate places that do the
> right thing either way, and only needs logic to decide whether to use the
> returned DMA addresses directly or ignore them if it knows they're
> overridden by its own IOMMU mapping.
I'd be happy to review patches for this.
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