[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20201016163318.GI5274@sirena.org.uk>
Date: Fri, 16 Oct 2020 17:33:18 +0100
From: Mark Brown <broonie@...nel.org>
To: "Ramuthevar,Vadivel MuruganX"
<vadivel.muruganx.ramuthevar@...ux.intel.com>
Cc: vigneshr@...com, tudor.ambarus@...rochip.com,
linux-kernel@...r.kernel.org, linux-spi@...r.kernel.org,
robh+dt@...nel.org, devicetree@...r.kernel.org,
miquel.raynal@...tlin.com, simon.k.r.goldschmidt@...il.com,
dinguyen@...nel.org, richard@....at, cheol.yong.kim@...el.com,
qi-ming.wu@...el.com
Subject: Re: [PATCH v1 4/6] spi: cadence-quadspi: Add QSPI support for Intel
LGM SoC
On Fri, Oct 16, 2020 at 05:31:36PM +0800, Ramuthevar,Vadivel MuruganX wrote:
> + depends on OF && (ARM || ARM64 || X86 || COMPILE_TEST)
> + {
> + .compatible = "intel,lgm-qspi",
> + },
This is an x86 SoC (or SoC series) - is it really going to use DT for
the firmware interfaces? It's not specifically a problem, just
surprising to see something other than ACPI. Or is the intention to use
PRP0001? There's a new comaptible here which wasn't really the use case
for PRP0001. Like I say not really a problem, just curious.
Download attachment "signature.asc" of type "application/pgp-signature" (489 bytes)
Powered by blists - more mailing lists